SU1443196A1 - Device for shaping frequency-manipulated signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the accuracy of the formation of frequency-modulated signals. The device contains pulse generator 1, controlled by rr 2, synchronizer 3, counters 4 and 9, adder 5, modulator 6, memory blocks 7 and 11, filter 8, subtraction unit 10, frequency divider 12 and g- p 13 pulses. The modulator 6 generates a voltage that, after passing through the adder 5, acts on Mr. 2, the output frequency-modulated oscillation. The goal is achieved by introducing a divider 12 and g-13, with the help of which, in the presence of errors, a mismatch signal is generated, which, acting on G-2, reduces its phase mismatch. Device on PP. 2 and 3 f-ly is distinguished by the performance of Mr. 13 and Divisor 12. 2 Cp. f-ly, 3 pcs. (Oh (L

Description

This invention relates to radio engineering and can be used to precisely form broadband signals.

The purpose of the invention is to increase the accuracy of the formation

Fig. 1 shows a structural electrical circuit of the device proposed; 2 and 3 are time diagrams ..

A device for generating frequency-modulated signals contains a pulse shaper 1, a controlled oscillator 2, a synchronizer 3, a first counter 4, an adder 5, a modulator 6, the first memory block 7, a filter 8, a second counter 9, a block 10, the second memory block 11, the frequency divider 12 and the generator of 13 pulses.

The pulse generator contains a memory block 14, a pulse shaper 15, a comparator 16, a digital-analog converter 17, and a counter 18.

The frequency divider contains a memory block 19 and a counter 20.

The device works as follows

The first output of the synchronizer 3 contains pulses (Fig. 2b), which set the counter 4, the modulator 6, the pulse generator 13 and the frequency divider 12 to the initial state. The period T, of these pulses, determines the modulation duration.

At the output of the modulator 6, a voltage is formed (FIG. 2a), which, passing through the adder 5, acts on the controlled oscillator 2, the output of which produces a frequency-modulated oscillation of the form (Fig. 26). U (t) U sinir if (-C -) + (tr), O-6 with 1 (1). Here and is the amplitude of oscillations; “- current time normalized to T; fC t) is the required modulation law; - C) - deviation from the required law.

Voltage (1) takes zero values at time points determined from the equation -t-J ((mp) m, m U, 1, ..., M (2). These values are fixed by shaper 1 of pulses, the output of which develops a pulse sequence (Fig. 2d). In the absence of errors, i.e. when () 0, the moments t are determined from the relation tf (t) m, (3)

In the cells of the memory block 7, the number codes are written (Hz-SVI - () / N, where N is an integer, (4), which are constant over time intervals (€ „, p, f„). The appearance of an output pulse driver 1 pulses leads to a change in the code at the input of memory block 7 and, consequently, to a change when the number is 0.

At the same time, the oscillation U (T) (Fig. 3a, solid line) also (Fig 2b) from the output of the controlled generator 2 is fed to the first input of the generator 13 pulses.

The pulse generator 13 works in the following way.

The state of the counter 18 determines the address of the memory cell of the memory block 14, the contents of which, transformed by the digital-to-analog converter 17, sets the threshold voltage (Fig. 3a, dashed line) of the comparator 16, the second input of the comparator-16 receives the oscillation (1) . When the value of and C L) is equal to the threshold value, a voltage drop is generated at the output of the comparator 16 (Fig. 36), the driver of the pulse generator 15. The pulses from the output of the driver 15 are fed to the output of the generator 13, and also change the state of the counter 18. and therefore, the threshold voltage at the first input of the comparator 16 "

The number N determines the number of pulses within any interval (.,

1) in the absence of errors, H (cG) 0, these pulses are formed in equiquotically more within the specified time interval cGy, „nSm + Tm-i, n

 1,2 ..., N (5). If () FD, then the pulses are formed at the moments (Fig. 3b), the same (Fig. 2e), other than (5), by the magnitude of the time error.

- The number of cells in the memory block 14 is equal to the product, and the counter size 18 must be no less than. In order to form a uniform sequence of pulses at times o, it is necessary that the cells D and sinir ((n) (6)) be recorded in the cells of memory block 14. Since from relations (3) and (5) and from (fig.Za) it follows that t. it is necessary that A, O for any w, while the signal transitions (1) through zero are the moments of error measurement.

The digital-to-analog converter 17 generates both positive and negative voltages at the output, so one bit of the output code of memory block 14 must be signed.

The code of the number is formed by a counter 9, the first input of which receives pulses from the output of the generator 13 (FIG. 3B), the same (FIG. 2d), and the second from the output of the frequency divider 12 (FIG. 3d) and block 11 memory Counter 9 counts the number of pulses at the output of the splitter 12 frequency. At the time of the appearance of the leading edge of the pulse at the output of the generator 13, the contents of counter 9 are overwritten in memory block 11, and at the time of the appearance of the trailing edge, the counter 9 is reset.

 At the output of subtraction unit 10, a temporal mismatch mnp -5 (FEG) is formed, which, having passed through the filter 8 and the adder 5, acts on the control oscillator 2 so that the phase mismatch - (C) is reduced.

To ensure high accuracy in the formation of frequency-modulated signals, the fulfillment of the condition

Tcfm 1 / f ",

(7)

where frti is the frequency of the pulses at the output of the splitter 12 frequency. The codes for S are given by

 „, TO.

(eight)

To provide the same relative error in the measurement of the temporal discrepancy.

 tpp

of all intervals (m-ip. p) the value of P (1 (, must be constant, or, equivalently, „must be inversely proportional to 6 .. However, due to the fact that the duration of these intervals is not a multiple of each other This condition is not exactly fulfilled. Reducing the values of f to the value of one order is provided by a frequency divider 12, the division ratio of which depends on the code at its fourth input, or, equivalently, at the input of memory block 19. The division value itself

written in the cells of memory block 19.

The clock pulses come from the first output of the synchronizer 3

 at the second input of counter 20, transforming at its output into frequency f ,. The output pulses of the generator 13 set the counter 20 to the zero state (fig, g).

Claims (3)

1. An apparatus for generating frequency modulated signals containing a synchronizer, the first output of which is connected to the first input of the first counter and to the input of the modulator, the output of which is connected to the first input of the adder, the output of which is connected to the input of the controlled generator, pulse shaper, the output of which is connected to the second input of the first counter, the output of which is connected to the entrance the first memory block, the output of which is connected to the first input of the - subtraction unit, the second input of which is connected to the output of the second memory block, the first input of which is connected. to the output of the second counter, the first input of which is connected to the second input of the second memory unit, the filter whose output is connected to the second input of the adder, and the output of the controlled generator is the output of the device, which is In order to improve the formation accuracy, a pulse generator and a frequency divider are introduced, the output of which is connected to the second input of the second counter, the first input of which is connected to the output of the pulse generator and to the first input of the frequency divider, the second input which is connected to the second output of the synchronizer, the first output of which is connected to the third input of the frequency divider and to the first input of the pulse generator, the second input of which is connected to the output of the controlled generator and to the input of the pulse shaper, with the output of the first counter connected to the fourth input of the frequency divider, and the output of the subtractor is connected to the input filter a 2. The device according to claim 1, characterized in that the generator The pulses comprise a serially connected counter, a memory unit, a digital-to-analog converter, a coparator and a pulse shaper, the output of which is connected to the first input of the counter and is the output of the pulse generator, the first and second inputs of which are respectively the second input of the counter and the second comparator input. 3. The device according to claim 1, characterized in that the frequency divider contains the connected memory block and the counter, the output of which is the output of the frequency divider, the first, second, third and fourth inputs of which are the first, second and third inputs of the counter, respectively, and the input of the memory block. one II I I I II I I I II I Illlllllinilllllllllillllllinillllll, FIG. 2 “; U but) f) “I) f)