SU1506464A1 - Linear unit of telemechanics system - Google Patents

Abstract

The invention relates to telemechanics and can be used in systems with a time division of signals with various formats of information packets transmitted to the communication line. The purpose of the invention is the expansion of the field of application due to the possibility of receiving information packages of various structures. The linear node contains a noise suppression unit 1, a generator 2, a clock synchronization unit 3, a sync pulse detector 4, pulse drivers 5, 6, first and second receivers 7 _-1 , 7 _-2 information signals, each of which includes switch 8, counter 9, multiplexer 10, address register 11, memory block 12, decoders 13, 14, elements OR 15-17, elements AND 18, 19, distributor 20. Detector 4 consists of a shift register 21, a setting unit 22 of a synchronization code and a comparator 23. Second driver 6 signal consists of a timer 24, the element OR 25, the element AND 26. In line This block is provided with automatic partitioning of data coming from the communication line into unified information frames with identification of the location of synchronizing parcels in them and subsequent input of information into the receiver. This allows you to receive information from telemechanics systems with different structures of information packages. 2 hp f-ly, 1 ill.

Description

V

(L

ate

4: About "

Sunt / cfc

3 clock synchronization, sync pulse detector 4, pulse formers 5, 6, first and second information signal receivers 7,, 7j, each of which includes switch 8, counter 9, multiplexer 10, address register 11, memory block 12, decoders 13, 14, elements OR 15-17, elements AND 18, 19, distributor 20. Detector 4 consists of a shift register 21, a sensor 22 of a synchronization code and a comparator 23. The second signal generator 6 consists of timer 24, element OR 23, element AND 26, The linear block provides automatic partitioning data from the communication line to unified information frames with the identification of the location of the synchronizing parcels in them and the subsequent input of information into the receiver. This allows you to receive information from telemechanics systems with different structures of information packages. 2 hp f-ly, 1 ill.

The invention relates to telemechanics and can be used in time-sharing networks with various information formats transmitted on the communication line.

The purpose of the invention is to expand the field of application by providing the possibility of receiving information messages of various structures.

The drawing shows a functional diagram of a linear node.

The line node contains a noise suppression unit 1, a generator 2, a block 3 synchronization synchronization unit, a sync pulse detector 4, a pulse generator 5 and 6, a first 7. and a second 7 information signal generator, each of which includes a switch 8, a counter 9, a multiplexer 10, a register 11 addresses, memory block 12, decipherors 13 and 14, elements OR 15-17, elements AND 18 and 19, distributor 20

Detector 4 consists of a shift register 21, a dial 22 with a 1-clock code, and a comparator 23.

The second shaper 6 signal consists of a timer 24, the element OR 25 and the element And 26.

Linear node works as follows.

Information from the communication line enters the input of unit 1. The output signals of unit 1, together with the signals from generator 2, arrive at unit 3, in which, at the moments of a change in the logic level in a received communication line

the sequence is inertia correction of the clock phase so as to align the clock edge with the midpoints of the reception intervals of each information signal.

The output signals of block 3, synchronized with respect to clock pulses from oscillator 2, are fed to register 21 of detector 4. The type and number of bits in the synchronization code, the transmission of which starts the transmission cycle of information transfer, do not match in different telemechanics systems. Therefore, the number of bits of the register 21 is chosen to be the largest number of bits of the synchronization code in the telemechanics systems that are intended to be connected to this system. The unit 22 determines the specific type of synchronization code to which the linear unit must respond. The unit is a switch in which, for example, the mode jumpers set the signals 1 and O for each of the bits of the synchronization code. The code from setpoint 22 is constantly compared by the comparator 23 with the current value of the code set in register 21. The code in the register changes as each next received signal from the communications line is entered into it. For data entry into the register are used

clock signals from the generator 2.

A signal is formed at the output of the comparator 23 if a code combination is set in register 21, which coincides with the code received from the setting device 22 and the corresponding synchronization code received in the telemechanic system connected to the linear unit. In the case when the number of bits in the synchronization code is smaller (for a particular telemechanical system) of the fixed number of bits pei iic / rpa .21, instead of the unused code bits of the setter 22, the numbers of the register 21 outputs are connected to the inputs of the comparator 23. conditions are created to adapt the universal detector A to the type of synchronization code without limiting the number of information bits (within a given maximum determined by the information capacity of the register 21 and the switching capacity Mi setter 22). The signal from comparator 23 of detector D is fed to input 3 of both receivers 7, and 7 (in connection with the identical structure and operation of the channels in the future, links are made only to 7). In the initial state, the signal 1 is formed at the output O of the distributor 20. This signal is fed to the input of the write resolution of the address register 11, in which the parallel code of the counter 9 is entered by the signal from the detector 4. Thus, the register 11 stores current address - counter code 9, at which the reception of the synchronization code is fixed. In the initial state of the distributor 20, the signal at the first input also allows the passage to the switch output of 8 clock signals from its first input coming from the input from generator 2. The clock signals correspond to the frequency of receiving signals from a source (not shown) from the communication line. Thus, the current states of the counter 9 correspond to the numbers of received information bits. The information bits of the received data sequence from the output of block 3 to the 4th input are sent to the information input of memory block 12, the address inputs of which are fed from the output of counter 9, to the enable input of recording mode — the signal from the output O of the distributor 20, and clocking - the signal from the output of the switch 8.

The synchronous data entry mode in the memory unit 12 continues until the fixed boundary of the information frame is fixed by the first decoder 13. The decoder 13 perceives the signals from the counter from the first inputs and adjusts to receive a certain number of data bits constituting one information frame. The number of bits in the frame should not exceed

information capacity of 1Z memory block. The second input to the decoder 13 is given an enable signal from the element OR 15, since in this mode one of its inputs receives a signal 1 from the output O of the distributor 20 (The signal from the decoder 13 through the first element 18, to which the second input gives a signal The output O of the distributor 20 enters through the output 5f to the input 6t of the second channel, ensuring the transfer of the distributor 20 of the second channel to the initial state (similarly to the signal from output 5, coming through the input 6, to the first input of the distributor 20, is brought to the beginning first state channel at the end of the reception of the information frame in the second channel).

The signal from the decoder 13 through the OR 16 element is fed to the second (counting) input of the distributor 20. As the third input of the distributor 20 is fed the enable signal from the 4th output, the signal from the OR 16 element switches the distributor 20 to the next position, forming a signal 1 at the 1st exit. By moving the distributor 20 to position 1, the mode of entering information into the first channel is completed, but at the same time the input of information into the second channel begins.

The first channel is set to the preparation mode, and then the output is received and information stored in it. In position 1 of the distributor 20, the signal from output 6 is fed to the first input of the imaging unit 6. Through the OR 25 and AND 26 elements, the incoming signal is fed to the output of the linear block. The information receiver (not shown) should respond to the received signal. Start the signal. Resolution that goes to both channels. In the channel that prepared the information, the distributor 20 is set to position 1. Therefore, a signal at the output of the second element AND 19 is formed in it. With this signal, the distributor 20 is transferred to position 2 through the ISH1 elements 16, thereby removing the previously generated Start signal. At the same time, reading data from the memory block 12 is enabled, and the counter 9 is set to the initial state by a signal from the OR element 17, repeating the signals of the OR element 16.

The speed of information output is determined by the frequency of the network from the second output of the generator 2, passing through the 2nd input and the switch 8 or the inputs of the counter 9 of the memory block 12. The output speed is set; taking into account the speed of the receiver information.

The order is followed by 1 output information: a series is identical to the installed one in the input mode, since in output mode the same counter 9, previously set in the initial state, is used. The information is read from the block; 12 memory and through the output 1 (1 li 1-, for the second channel) enters the shaper 5. Shaper 5 is a coaxial that passes information from inputs 1 ,, 2, C or 2 ,, to the output when the signal arrives to one of the corresponding information inputs 3 ,, 4 ,, 3 or 4 2 controls. In this mode, a control signal is fed to input 3 of input generator 3, since the distributor 20 of the first channel is set to gct. 2. Therefore, the information of the linear unit is scared 1 by the pychol; and input to the iio driver input 1. To synchronize the input of information into the receiver, the signals of generator 2 should be used, and the start of reception is defined (; d, it is due to the removal of the Signal Start).

After outputting all the bits of the information frame, but si-tal from t; decipher 13 (its operation is allowed by the signal from output 2 of distributor 20, passed through the ILTDI element 15) through the CHI element 16 distributor 20 nepeBo / uiTCH to position 3. At position 3 spreading the receiver 20 (not shown) enters data from register 11, identifying the location of the synchronization code within the already entered information frame. Using the multiplexer 10, the parallel register code 11, which arrives at the second inputs of the multiplexer 10, is converted into serial synchronously with the arrival of address signals from the counter 9 output to the first inputs of the multiplexer 10. The enable input of the multiplexer 10 receives a signal from the output 3 of the distributor 20. 11 sequential code from

0 5 0 5

0

0

five

the multiplexer 10 through the output 2 enters the input of the imaging unit 5, which passes it to the Extreme Information, since the control input 5 is given a signal from the output 4.

The order of register code 1 1 is set by a counter 9 preset to the initial state by a signal from the element OR 17. The second decoder 14 fixes the completion of the code output from the register 11, using for this the code signals arriving at its first inputs from the counter 9 (so, if block 12 is designed for I / O 256 bits, register 11 contains 8 bits, and decoder 14 must fix the code combination corresponding to the input of 9 eight clock signals into the counter). In this mode, the operation of the decoder 14 is resolved by a signal 1 received at its second input from the 3rd output of the distributor 20. By a signal from the output of the decoder 14 passing through the IPI element 16, the distributor 20 is transferred to position 4. The signal from the 4th output of the distributor A split 20 is fed to its third input, further operation, and a counter 9 with a signal from the element LiTlH 17 is kept in the initial state. This completes the data input / output cycle in the first channel, and it is put into standby mode at input 6 (from output 5 7. of receiver 7), which determines the completion of the input frame of the information frame to receiver 7.

The marked alternate operation of both channels of the linear block continues until the absence of synchronization code in the data received from the communication lines for a time longer than the set threshold is detected. The time threshold of the synchronization code is set by timer 24, which is part of the forms of the lover 6. The timer is reset to each signal of the comparator 23, which fixes the reception of the synchronization code. In the pauses between the arrival of signals from the comparator 23, the timer calculates the signals from generator 2. When the signal at the timer output appears, the operation of element I 26 is blocked and, consequently, the formation of trigger signals — the line unit is placed in the receive standby mode.

.-

sync code. By adjusting the time threshold of the timer 24, the linear unit is adapted to the information transmission algorithm in the particular telemechanic system.

In the linear unit, the data coming from the communication line is automatically divided into unified information frames with identification of the location of the synchronizing data in them and the subsequent input of information into the receiver. This allows you to receive information from telemechanics systems with different

Claims (3)

1. A linear node of the telemechanic system containing a clock synchronization unit, a generator, the first output of which is connected to the first input of the clock detector, the first information signal receiver including a distributor, the first output of which is connected to the input of the first decoder, the memory block, the first and second And, the first and second outputs of the distributor of the first receiver of the information signal are connected to the first and second inputs of the first pulse shaper, respectively, characterized in that, in order to expand use of the application area due to the possibility of receiving information from different structures, a suppression unit is inserted in it, a second pulse shaper, a second information signal receiver, implemented similarly to the first one, and in each information signal receiver — a switch, a counter, a multiplexer, an address register, the second decoder and the OR elements, the input of the interference suppression unit is the first input of the node, the output of the interference suppression unit is connected to the first input of the clock synchronization unit, the second input to combined with the first inputs of the sync pulse detector of the second pulse driver and switches of the first and second information signal receivers, the output of the clock synchronization unit is connected to the input of the generator, the second input of the sync pulse detector and the first input of the memory block of each information signal receiver, the output of the sync pulse detector is connected to the first 25 yu 15 20 30 35 40 45 d the register of the address of each receiver of the information signal and the second input of the second pulse shaper, the third and fourth inputs of which are connected to the third outputs of the distributors of the first and second receivers of the information signal, respectively, in which the output of each switch is connected to the first input of the counter and the second memory input ti, the outputs of the counter are connected to the corresponding information inputs of the multiplexer, the address register, the memory block and the decoders, the outputs of the address register are connected to The corresponding address inputs of the multiplexer, the outputs of the first and second decoders are connected respectively to the first and second inputs of the first RSHI element, whose upstream is connected to the first inputs of the second OR element and the distributor, the fourth outlet of which is connected to the first inputs of the first ANDy3 third element, and the second inputs of the switch and the address register, the third input of the memory unit, the fifth output of the distributor is connected to its second input and the second input of the second OR element, the output of the third OR element one with the input of the second decoder, the output of which is connected to the second input of the first element AND, the output of the second element AND is connected to the third input of the first element OR, the second output of the distributor is connected to the second input of the third element OR, the first output of the distributor is connected to the second element OR is connected to the second input of the counter, the third output of the distributor is connected to the first input of the second element AND, the second input of which in each information signal receiver is the second input of the outputs of the memory block, the multiplexer and the first and second outputs of the distributor of the second information signal receiver are connected to the third, fourth, fifth and sixth inputs of the first pulse shaper, respectively; the outputs of the memory block and multiplexer of the first information signal receiver are connected to the seventh and eighth inputs the first pulse shaper, respectively, the outputs of the first elements And the first and second receivers of the information signal connected to the third inputs of the distributors, respectively first and second receivers of the information signal, the third inputs of the switches are connected to the second vkodom generator, the outputs of the first and second pulse shapers are respectively first and second output node. 2. The linear node of claim 1, wherein the sync pulse detector contains a comparator, a synchronization code setter, a shift register, the first and second inputs of which are respectively the first and second inputs of the detector, the output of the shift register is connected to the first the input of the comparator, the second input of which is connected to the output of the master clock sync code; the output of the comparator is the output of the detector. 3. The linear node according to claim 1, about tl and - parts in that the second driver contains an AND element, an OR element and a timer, the first and second the inputs of which are respectively the first and second inputs of the former, the timer output is connected to the first input of the AND element, the output of which is the output of the former, the second input of the AND element is connected to the output of the OR element, the first and second inputs of which are respectively the third and fourth shaper inputs.