SU1499484A1 - Minimum asymmetry double inverter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing and microprocessor technology, in systems of enhanced performance. The aim of the invention is to reduce the asymmetry of the output signals by applying feedback between the output transistors. Dual inverter contains an input circuit, two inverters, the base of the additional transistor is connected to the base of the output transistor of the second inverter, the emitter is connected to the common bus, the collector is connected to the cathode of the diode, the anode of which is connected to the base of the transistor, the collector of which is connected to the inverse output bus and the emitter of the composite transistor and its emitter is with the collector of the output transistor of the first inverter. The diode anode is connected to the power rail via a resistor. 1 il.

Description

The invention relates to a pulse technique and can be used in high-performance computing.

The aim of the invention is to reduce the asymmetry of the output signals by applying feedback between the output transistors of the circuit.

The drawing shows the electric circuit in principle, a dual inverter circuit with minimal asymmetry.

Minimal asymmetry dual inverter contains input bus 1, -inverse output bus 2, forward output bus 3, power supply bus 4, common bus 5, first transistor 6 and phase-split transistor 7 of the first inverter, whose bases are connected together and connected to the emitter input transistor 8, the anode of the first.

Schottky diode 9 and through the seventh resistor 10 to the common bus 5 and the anode of the second Schottky diode 11, the cathode of which is connected to the cathode of the first Schottky diode 9, input bus 1 and the cathode of the third diode 12, the anode of which is connected to the base of the input transistor 8 and through the eighth resistor 13 to the power supply bus 4 and the first terminal of the ninth resistor 14, the second terminal of which is connected to the collector of the input transistor 8, the emitters of the first 6 and phase-separating 7 transistors of the first inverter are connected to the base of the output transistor 15 of the first inverter and through the first p ican 16 to the common bus 5, and the emitter of the output transistor 15 of the first inverter, a collector of the first transistor 6 is connected to the base of the phase separation Transistor

WITH

with

4 :: 00 4

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pa 17 of the second inverter and through the second resistor 18 with the power supply bus 4, the collector of the phase separation transistor 7 of the first inverter is connected to the base of the Second transistor 19 and through the third resistor 20 with the power bus 4 and collectors of the second 19 and third 21 transistors, the base of the third transistor 21 connected to the emitter of the second transistor 19, and its emitt6 p to the inverse output bus 2 and the collector of the fourth transistor 22, the emitter of which is connected to the collector of the output transistor of the first inverter 15, the emitter of the phase separation transistor The mouth 17 of the second inverter is connected to the base of the output transistor 23 of the second inverter and the base of the additional transistor 24, the emitters of which are connected and connected to the common bus 5 and through the fourth resistor 25 to the emitter of the phase separation transistor of the second inverter 17 transistor 26 and through the fifth resistor 27 to the power supply bus 4, the collector of the fifth transistor 28 and the collector of the sixth transistor 26, the emitter of which is connected to the base of the fifth transistor 28, the emitter of which is connected to direct discharge bus 3 and the collector of the output transistor 23 of the second inverter.

additional transistor collector

Pa 24 is connected to the cathode of the diode 29, the anode of which is connected to the base of the fourth transistor 22 and through the sixth resistor 30 to the power bus 4.

Dual inverter works as follows ..,

.If low voltage is applied to input bus 1, diode 12 is open and transistors 8, 6, 7 and 15 are closed, because there is no current in the base circuits of these transistors. A high voltage level is formed on the inverse output bus 2, defined by open transistors 19 and 21. A high voltage level on the collector of the closed transistor 6 causes current to appear in the base circuit of the transistor 17. Transistor 17. opens, the current begins to flow through the resistor 27, which forms the base current of the drive chips 23 and 24. The open transistor 23 forms a low voltage level on the direct output spike.). Discoveries Transsips 4 and sip

u 5 20 25 30

35

..

.

five

the shifted diode 29 forms a low voltage level at the base of the transistor 22, equal to

AUyy (Et4

where and is the voltage at the base of the transistor 22; 43 - voltage across a direct-displaced Schottky diode 29; Ujj324 voltage between the collector ;; rum and emitter OPEN

transistor 24.

Therefore, if low voltage is present on bus 1 on bus 2, a high voltage level is formed, and bus 3 has a low voltage level. When the voltage on the bus 1 changes from a low level to a high diode 12, it closes, the current from bus 4 passes through the resistor 13 to the base of transistor 8, transistor 8 opens, current flows through the resistor 14 to base transistor% 6 and 7. Transistors. 6 and 7 open, in collector circuits, these transistors appear currents, defined by resistors 18 and 20, which, entering the base of transistor 15, open it. Thus, a low voltage level is formed on the collector of the transistor 15. However, at the base of the transistor 22, the voltage level U, detected by the open transistor 24, the emitter of which is connected to the common bus 5 and the shifted diode 29, is insufficient for unlocking it, and thus, on the output bus 2 continues to be absent, low voltage level Turning off the transistor 17 leads to turning off the transistor 23, as well as turning off the transistor 24, the collector voltage of which monitors the voltage variation on the collector of the transistor 23, i.e. to - output bus 3. When a transistor 24 at the collector reaches a voltage equal to

Ua UK3ts U53 "-UA" "where and is the voltage at the collector

transistor 24;

 voltage between the collector and the emitter of the open transistor 15;

Ugj 21 is the voltage of the pre-displaced block — the emitter is transis: 1О1 l 22;

and. -J-, for example, n.i of the Directive YANOD (;) IJor-1-CI,

The base of the transistor 22 begins to receive current from the power supply bus 4 through the resistor 30, leading to the opening of the transistor 22 and the setting of a low voltage on the output bus 2. On the output bus 3, this sets a high voltage level defined by open transistors 26 and 28. Thus, the occurrence of a low voltage level on the output bus 2 is matched in time with the appearance of a high voltage level on the output bus 3. Anti-call The diode 11 in the circuit is designed to limit the amount of negative interference at the input of the circuit. Diode 9 and resistor 10 form a turn-off circuit of transistor 6 and 7, Resistors 16 and 25 provide a turn-off circuit for transistors 15 and 23.24, respectively.

Thus, the introduction of feedback between the output transistors leads to the fact that a low voltage level at the inverse output of the circuit begins to form when the direct output of the circuit goes from low to high, therefore, the asymmetry between the signal on bus 2 and the signal is eliminated on bus 3, when the input signal on bus 1 passes from a low to a high voltage level.

Claims (1)

Invention Formula A minimum asymmetry dual inverter containing a diode, an additional transistor, a first transistor and a phase-separation transistor of the first inverter, whose bases are connected to the input circuit, and the emitters are connected to the base of the output transistor of the first inverter and through the first resistor to a common bus and emitter the output transistor of the first inverter, the collector of the first transistor is connected to the base of the phase separation transistor of the second inverter and through the second resistor to the power bus, the collector of the phase separation transistor of the first inverter is connected to the base of the second transistor and Q third resistor - with a power bus and collectors of the second and third transistors, the base of the third transistor is connected to the emitter of the second transistor, and its emitter is connected to the inverse output bus and collector of the fourth transistor, the emitter of which is connected to the output transistor of the first inverter, emitter phase separation transistor second The Q inverter is connected to the base of the output transistor of the second inverter and through the fourth resistor to the common bus and emitter of the output transistor of the second inverter, the collector of which is connected to the direct output width and emitter of the fifth transistor whose base is connected to the emitter of the sixth transistor, ::; The collector is connected to the power bus and the collector of the fifth transistor, and the base is connected to the collector of the phase separation transistor of the second inverter and through the fifth resistor to the power bus and the first output of the sixth resistor, In order to reduce the asymmetry of the output signals, the base of the additional transistor is connected to the base of the output transistor of the second inverter, the emitter is connected to the common bus and the collector is connected to the cathode of the diode, the anode of which is connected to the base of the fourth transistor and the second output of the sixth resistor five 0