JPS605091B2 - High speed comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed comparator circuit, and more particularly to a high-speed comparator circuit that can be integrated at a high density for IC use by reducing power consumption.

Recently, integrated circuit manufacturing technology has been developing rapidly.
It has become possible to integrate various circuits at a very high density. In other words, an advantage of integrated circuits is that a desired circuit can be provided in an ultra-miniaturized manner. However, this miniaturization technology is not necessarily without problems;
However, when a large number of circuits are mounted on a large device, the disadvantage that the mounting density is limited if the power consumption of the circuits is large has not been solved yet. The present invention focuses on such problems and enables a comparison circuit, which has conventionally been widely used as a component of an A-D converter, to output a signal having a current drive ability and a signal having a current sink ability. It is an object of the present invention to provide a high-speed comparison circuit that is capable of high-speed operation and eliminates wasteful power consumption during high-speed operation, thereby achieving high-density integration.

Such a circuit consists of multiple non-saturated differential amplification stages and an output stage that outputs logic circuit level signals, and is configured so that the output stage does not consume power for a certain period of time during the process in which the output of the output stage is inverted. It can be obtained by That is,
According to the present invention, a first rhombic amplification stage, second and third differential amplification stages respectively connected to two differential output terminals of the differential amplification stage, a current sink transistor, and a current sink transistor are provided. two differential output terminals in the second differential amplification stage, one of which is connected to the current sink transistor of the first output stage. The other side is connected to the current sink transistor of the second output stage, and one of the two differential output terminals of the third differential amplifier stage is connected to the current sink transistor of the second output stage. The other of the external transistors is connected to the current drive transistor of the first output stage, and between the second and third reed amplification stages and the first and second output stages. connects a clamp circuit, and furthermore, in the process of inverting the output of each output stage of the second and third differential amplification stages, both the current sink transistor and the current drive transistor in each of the output stages are turned off. A high-speed comparison circuit is obtained, which is characterized in that it is configured such that there is a period in which .

Hereinafter, embodiments of the present invention will be described with reference to the drawings on the premise that they will be manufactured for IC use.

FIG. 1 is a diagram showing a schematic configuration of a high-speed comparator circuit according to the present invention. In particular, it is capable of outputting a signal having a current driving ability and a signal having a current sinking ability as output signals. It consists of differential amplification stages 1, 2, and 3, and output stages 4 and 5 for obtaining outputs at the logic circuit level. The differential amplification stage 1 has a non-inverting input terminal 6 to which a difference signal is input, an inverting input terminal 7, and difference output terminals 8 and 9,
The differential output terminals 8 and 9 are the differential input terminals 10 and 11 of the differential amplification stage 2 and the differential input terminals 14 and 15 of the differential amplification stage 3.
are connected to each. Further, the inverting output terminal 13 of the differential amplifier stage 2 is connected to the input terminal 18 of the output stage 4, the non-inverting output terminal 12 is connected to the input terminal 21 of the output stage 5, and the inverting output terminal 17 of the differential amplifier stage 3 is connected to the input terminal 18 of the output stage 4. is connected to the input terminal 222 of the output stage 5, and the non-inverting output terminal 16 is connected to the input terminal 19 of the output stage 4. With such a connection, when a difference signal is input to the input terminals 6 and 7 of the differential amplifier stage 1, the output stage 4 outputs a non-inverted output from the output terminal 20,
The output stage 5 outputs an inverted output from the output terminal 323. Note that "symbol 24 is a common ground terminal, and 25 and 26 are power input terminals. Now, a differential input transistor is used in each of the differential amplification stages configured in this way,
It is clear that by operating this differential input transistor only in the active region, the circuit can be operated at high speed. In this embodiment, this is done by clamping the amplitude of the input voltage with a Schottky diode, and a specific example thereof will be explained with reference to FIG.

FIG. 2 is a diagram showing a specific circuit configuration from differential amplification stages 2 and 3 to output stages 4 and 5 in FIG. Current sink transistor (that is, functions to absorb current from the load side of the power terminal 20 in a conductive state) Tr4
A and a current drive transistor Tr4B (that is, it functions to supply current to the load side of the power terminal 20 in a conductive state) connected to the input terminal 19, and the output stage 5 has a base terminal connected to the input terminal 19. It consists of a current sink transistor Tr5A connected to the input terminal 21 and a current drive transistor Tr5B connected to the input terminal 22.

In the output stage 4, the emitter terminal of the transistor Tr48 is grounded to the common ground terminal 24, the collector terminal of the transistor Tr48 is grounded to the positive power input terminal 25, and the collector terminal of the transistor Tr4 and the emitter terminal of the transistor Tr48 are grounded. The same applies to the output stage 5. Furthermore, Schottky diodes 41 and 42 are provided between the common ground terminal 24 and the output terminals 12 and 13 of the differential amplifier stage 2, respectively, to clamp the amplitude of the output voltage and to operate the differential amplifier stage 2 in the active region. Schottky diodes 44 are inserted between the bias terminal 43 and the output terminals 16 and 17 of the differential amplifier stage 3 and between the common ground terminal 24 and the output terminals 16 and 17, respectively.
, 45, 46, and 47 are inserted to clamp the amplitude of the output voltage and to operate the differential amplifier stage 3 in the active region. Of course, the clamp circuit is not limited to a Schottky diode. As described above, a comparator circuit that operates at high speed can be realized by using a multi-stage configuration of non-saturated differential stages.
When the transistors Tr48, T and B are in a conductive state, an output signal having a current driving capability is obtained, and when the transistors Tr4A, T and A are in a conductive state, a signal having a current sinking capability is obtained. It is impossible to eliminate unnecessary power consumption with this alone, and the configuration and conditions for making this possible will be explained with reference to FIGS. 3 and 4.
FIG. 3 is a circuit diagram showing a simplified configuration of a part of the differential amplifier stages 2 and 3 and the output stage 4 in order to explain the operation of the output stage 4 in FIGS. 1 and 2. The output stage 5 operates in a similar manner, so a description thereof will be omitted.

First, the reed amplification stage 2 is inserted and connected between a current source 2A having one end connected to the negative power input terminal 26, a current source 2B having one end connected to the positive power input terminal 25, and these current sources. The differential amplifier stage 3 similarly includes current sources 3A, 3B and an electronic switch Tr3c.

A differential output signal 27 from the differential amplifier stage 1 is applied to the electronic switches Tr2c and Tr3c as a driving signal, and the electronic switches Tr2c and Tr3c open and close in opposite phases. Reference numerals 51 and 52 indicate the parasitic capacitance generated between the insulating region of the integrated circuit and the collector region of the electronic switch, or the composite capacitance when additional capacitance is added to the parasitic capacitance.

Now, in this circuit, if the transistors Tr4A and Tr48 similarly become conductive when the output to the output terminal 20 is inverted, current will flow between the terminals 24 and 25, resulting in wasted power consumption. That will happen.

The present invention takes this point into consideration, and the transistors Tr4^ and T
This arrangement is such that the LBs do not operate at the same time, and this will be explained with reference to FIG. 4, which shows the output signal waveforms of each part. In the circuit of FIG. 3, when the output from the differential amplifier stage 1 is at the "mountain w" level before the point L as shown in FIG. 4, the electronic switch Tr2c is closed and the electronic switch Tr3 is closed.
c is in an open state. Therefore, at this point, the output signal 29 from the output terminal 13 of the differential amplifier stage 2 is at the "mountain w" level and the transistor Tr4^ is in a non-conducting state, and the output signal from the output terminal 16 of the differential amplifier stage 3 is 28 is at the "Hj turtle" level and the transistor Tr48 is in a conductive state. However, when the signal 27 is inverted at time t, the signal 29 from the differential amplifier stage 2 changes from "LoW" to "
The signal 2 from the differential amplifier stage 3 shifts to High' level.
8 transitions from "High" to "LoW' level. Here, the transition level 31 of transistor Tr small, Tr4B
If the transition timing from ``High'' to ``LoW'' level is set earlier than that shown in the figure, the signal 29 will reach the transition level 31 from the time when the signal 28 reaches the transition level 31. The period up to the point of arrival,
The transistors Tr4A and Tr group constituting the output stage 4 are both "off", and during this period the output stage 4 does not consume power, and its output signal 30 is at the "off" and "off" intermediate level 32 for a certain period of time.

Similarly, when the levels of the signals 28 and 29 change based on the inversion of the signal 27 at the time point, as shown in the figure, "
If the transition from "High" to "Low" level occurs first, the output signal 30 can be kept "off" and "off" for a certain period of time without consuming power in the output stage 4 during the period from t5 to t6.
It may be at an intermediate level 32. This is possible by satisfying the following conditions:
Let me explain this. Electronic switch Tr2c of differential amplifier stage 2
The voltage amplitude from the inversion output terminal 13 due to inversion operation is △V
, and the voltage amplitude from the non-inverting output terminal 16 due to the inverting operation of the electronic switch Tr of the differential amplifier stage 3 is ΔV2, and the current values of the current sources 2A, 2B, 3A, and 3B are 12^ and 128, respectively. , 13^, 13B.

Further, when the values of the capacitors 51 and 52 are respectively C and C2, during the transition period when the electronic switches Tr2c and Tr are inverted by the differential output signal 27 of the differential amplification stage 1, the differential amplification stages 2 and 3 The transient operation of the electronic switch (switch closing) that causes the output to shift to the “LoW” level is “Hi bait”.
The conditions for ensuring that the transient operation (switch opening) of the electronic switch that causes the transition to the current level is always preceded are approximately expressed by the following equation. In other words, the output terminal 1 of the differential amplifier stage 3
The conditional expression for the fact that the time for the output from the output terminal 13 of the differential amplifier stage 2 to shift to the "Hi" level is longer than the time for the output from the differential amplifier stage 2 to shift to the "Hi" level is △v2/pole. Spicy △v. /Koto...■, and the output from the output terminal 16 of the differential amplifier stage 3 is “H
The conditional expression for the long time to transition to "high" level is △
v,/Hitsugokoku△v2/station...■.

From the formulas ■ and ■, △V2 128 △V, 13A-13B ・C2<C. <Zenham≧・Toyozoza・C2...■138
o is obtained, and the comparison circuit shown in Fig. 1 is operated at high speed by the differential amplifier stages 2 and 3, the output stages 1 and 2, and the Schottky diode-based clamp circuit that satisfy this formula (■), and the output is A signal with current drive capability and a signal with current sink capability can be output from the terminal, and the average power consumption in the output stage can be significantly reduced.

This is because, whereas conventional C-MOS logic circuits, for example, have the disadvantage that the speed-power product increases significantly as the operating frequency of the logic circuit increases, the differential amplifier stage array according to the present invention has a (PJ/.a) The circuit can be such that it has the following speed-power product. FIG. 5 is a circuit diagram showing the overall configuration of the comparison circuit according to the present invention.
Descriptions of parts that are the same as reference numerals in the figures will be omitted.

51 and 52 are load resistances of the differential input transistors Tr, A, Tr, and B in the differential amplification stage 1, and the transistors Tr, Tt2o, and Tr3c, Tr3 in the differential amplification stage.

The resistance value is selected within a range that does not saturate. Current source 55
is used to DC bias the differential amplifier stage 1, and diodes 53 and 54 are inserted to obtain an appropriate differential output potential level. By integrating such a configuration,
The comparison result of the differential input signals input to the differential input terminals 6 and 7 can be taken out from the output terminals 20 and 23 as a differential output signal with current drive capability or current sink capability, and even during high-speed operation, the power Since consumption can be kept low, an integrated circuit device that can be mounted in high density can be obtained.

FIG. 6 is a diagram showing another embodiment of the present invention, and shows another example of the differential amplification stage 1 which has a high gain and is designed not to saturate the differential amplification stages 2 and 3. It is a circuit diagram.

That is, Schottky diodes 55 and 56 are inserted to clamp the differential output of the differential amplifier stage 1, and active load transistors Tr,c, and Tr,c, are inserted as loads for the differential input transistors Tr,^, Tr,B. In order to use the transistors Tr and D, the bias current thereof is supplied from one end 59 of the current source 2A of the differential amplifier stage 2.

Such a differential amplification stage increases the stability of the comparison circuit and is effective in increasing the comparison accuracy.

FIG. 7 is a circuit diagram 4 showing a third embodiment of the present invention, which is a basic inverter circuit using an active differential amplifier stage between differential amplifier stage 1 and differential amplifier stages 2 and 3. 60,70,8
0 is inserted to obtain the desired gain, the level is shifted by the level shift diodes 90 and 91, and the pre-trigger signal, which is currently effective in high-speed logic circuits, is inserted at any position in the inverter circuits 60, 70, 80. A high-speed comparator circuit that can be taken out from the circuit is shown.

92 applies an appropriate bias potential to the inverter circuits 60 and 70;
, 8・0 is shown.

Note that the resistors used in each inverter circuit can be ordinary diffused resistors, and furthermore, there is an advantage that so-called pinch resistors can be used to reduce the chip area of the integrated circuit. that's all,
As explained above, according to the present invention, in a comparator circuit capable of outputting a signal with current drive capability and a signal with current sink capability, wasteful power consumption in the output stage due to high-speed operation is eliminated. This enables high-density integration when mounted as an IC, and
We can provide an optimal high-speed comparison circuit for

[Brief Description of the Drawings] Fig. 1 is a diagram showing a schematic configuration of a high-speed comparison circuit according to the present invention, and Fig. 2 is a diagram showing a circuit configuration between the differential amplification stage and the output stage in Fig. 1. FIG. 3 is a circuit diagram schematically showing a part of the differential amplification stage and output stage in FIG. 1, and FIG. 4 shows the output signal of the differential amplification stage and the output signal of the output stage in FIG. 5 is a diagram showing an actual circuit as an example of the configuration shown in FIG. 1, and FIG. 6 is a diagram showing another implementation of the differential amplifier stage 1 shown in FIG. FIG. 7, which shows an example, is a circuit diagram showing another embodiment of the present invention. The reference numbers in the drawings are as follows. 1, 2, 3: Differential amplification stage, 4, 5: Output stage, 6, 7: Differential input terminal, 20, 23: Output terminal, 24: Common rear terminal, 25, 26: Power input terminal, 43 : Bias terminal,
41, 42, 44-47: Schottky diode, T
r4A, Tr5A: Current sink transistor, Tr4
B, Tr5B: Current drive transistor, 2A, 2
B, 2E, 3A, 3B, 3E: current source. Figure 1 Figure 2 Figure 3 Younger brother Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1 A first differential amplification stage, second and third differential amplification stages respectively connected to two differential output terminals of the differential amplification stage, a current sink transistor, and a current drive transistor. and two differential output terminals in the second differential amplification stage, one of which is connected to a current sink transistor of the first output stage, and the other is connected to a current sink transistor of the first output stage. The two differential output terminals of the third differential amplifier stage are respectively connected to the current sink transistors of the second output stage, and one of them is connected to the current drive transistor of the second output stage, and the other is connected to the current drive transistor of the second output stage. are respectively connected to the current drive transistors of the first output stage, and the second and third differential amplifier stages are connected to the current sink transistors of the respective output stages in the process of inverting the outputs of the respective output stages. A high-speed comparison circuit characterized in that it is configured such that there is a period in which both current drive transistors are off.