SU1499358A1 - User to communication channel interface - Google Patents

Abstract

The invention relates to computing and can be used in the construction of data exchange systems between local and remote subscribers and digital computers. The aim of the invention is to increase the speed and reliability of data exchange. The devices contain a receive register, a transmit register, a control register, a checksum register, a status register, a data register, a bit counter, a byte counter, two time counters, two triggers, a receive trigger, two multiplexers, three control decoders, a comparison unit, an adder, pause counter, array end decoder, pulse distributor, delay element, one-shot, thirteen AND elements, nine OR elements. 6 Il.

Description

The invention relates to computing and can be used in the construction of data exchange systems between local and remote subscribers and digital computers.

The aim of the invention is to increase the speed and reliability of data exchange. .

Data transfer between subscribers, which may be computers or subscriber stations, is carried out via a physical circuit, or through multiplexing equipment, with sequential codes. The unit of exchange is a data array, which consists of marker information and service data patterns. Marker codograms determine the beginning and end of the array transfer.

data, service codograms - the number of information codograms in the array and the checksum of information codograms of the data array.

The device for interfacing during the operation implements two modes of operation: reception of a data array and transmission of a data array.

At the beginning of operation, the device is; It is in readiness to receive data. When the first bit of the codogram arrives from the communication channel, the device is switched to the mode of receiving an array of data. In this mode, the first and second marker codes that identify the beginning of the data exchange are received. In the process of receiving these codograms, their correctness is monitored, and if an error is detected in the codogram

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the communication channel is rejected and the formation of the state word is carried out, which can then be used by the subscriber to assess the situation, and the device is transferred to the initial state of the reception mode,

In the event that the marker codograms are received correctly, a service codogram is received that determines the length of the information part of the data set, taking into account the checksum codogram.

In the following, information codograms are received by the device. The interaction of the subscriber with the interface device is realized in accordance with the polling mechanism. In the process of receiving information codograms in the device, a checksum is calculated.

When the reception of information codograms is completed, the device receives a codogram of the checksum, checks the received and accumulated checksums and generates the corresponding status word. The last coding pattern is received, after which the device is transferred to the initial state of the reception mode. Marker codogram is monitored as described above.

In the course of data exchange, each received codogram is transmitted by the device to the communication channel, and the transmitting device controls the quality of the data exchange. In addition, the device implements two levels of monitoring the state of the communication channel in terms of the communication delay time. At the first level of control, the time of reception of the codogram is calculated, and at the second level, the time in the pauses between the codograms is counted.

In case of violation of the control conditions by the device, a word of state is formed, corresponding to the situation that has occurred. If necessary, a device for cyclic control and coding of information codograms can be used between the interface device and the subscriber.

The synchronization sequences when receiving codograms are formed by linear blocks that are included at the channel input of the device and are not included in the description of the device in question.

If it is necessary to transfer data, the subscriber switches the device to the data transfer mode. In this mode, the device, under the influence of control signals received from subscribers, forms and transmits two marker codograms to the communication channel, and then performs

the transfer of information entered into the device by the subscriber. The control of the transmitted data is carried out similarly to the reception mode. - echoing of the interface of the subscriber of the communication subscriber. Upon completion of the transmission of the information part of the data array, the device generates a marker codogram and is switched to receive mode after receiving confirmation of it.

The device provides the ability to exchange data over non-switched and dial-up communication channels. This effect expands the field of application of the device. Improving the reliability of data exchange is achieved by ensuring that the communication channel is monitored before each use for data exchange using marker codograms, as well as the ability to control link hangs and communication channel failures in the data exchange process.

Figure 1 and 2 shows the functional diagram of the device; on fig.Z - functional skemy time counters and pulse distributor; Figures 4-7 of the algorithm for operating the device in the main modes.

The device contains (FIGS. 1 and 2) reception register 1, transmission register 2, control register 3, checksum register 4, status register 5, data register 6, 7 bits counter, 8 bytes counter, first 9 and second 10 time counters , the first 11 and second 12 triggers, the trigger 13 reception, the third 14,. The first 15, the second 16,. The ninth 17, Fifth 18, The tenth 19, The thirteenth 20, The twelfth 21, The eleventh 22, Fourth 23, Sixth 24, seventh 25 and eighth 26 elements And, fifth 27, eighth 28, second 29, seventh 30, first 31, third 32, ninth 33, fourth 34 and sixth 35 elements OR, first 36 and second 3 7 multiplexers, second 38 and first 39 control decoders, comparison unit 40, adder 41, pause counter 42, delay element 43, array end decoder 44, third control decoder 45, one-shot 46, pulse distributor 47, information input 48.1 and group information inputs 48.2 of the device, first 49.1 and second 49.2 device sync inputs, group of device control inputs 50, second 51.1 and first 51.2 device reversal inputs, sync output 52.1 and device information output 52.2, group of information outputs 53 , the output 54 of the device interruption signals, the setup input 55 and the output 56 of the first time counter 9, the second 57 and the first 58 start inputs, the setup input 59 and the output 60 of the second time counter 10, the first 61 and the second 62 start inputs, allowing the output 63, the second sync output 64, permitting output 65, third synchronizing output 66 of distributor 47, output 67 of comparison unit 40

The first time counter 9 contains a trigger 68 and a counter 69.

The second counter 10 time contains the trigger 70 start and the counter 71,

47 pulse distributor

there is a trigger 72 trigger, a counter 73, a shift counter 74, a decoder 75, a one-shot 76, a 77-delay element and an And 78 element.

Receive register 1 is intended for recording and storing data from a communication channel in a sequential code and is a shift register. The data record is gated with a pulse arriving at the synchronous input of the register. After writing the next data bit, the contents of the register are shifted by one bit.

Transmission register 2 is for recording and storing data intended for transmission to a communication channel in a sequential code. When data is transmitted to the communication channel, a single potential is established at the input E of the register, allowing the content to be shifted under the control of the clock pulses supplied to the input CE of the register 2.

Register 3 control is designed to store the value of the current contact 1499358

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the total amount of the data array generated in the process of receiving data from the communication channel.

Checksum register 4 is designed to record and store a word that determines the value of the checksum of the data array transmitted over the communication channel.

The status register 5 is for recording and storing error signals in the operation of the device, as well as device status signals and data. The single (zero) zero-state state of the 5 state register corresponds to the feature: new (old) data on the data 6 register. A single (zero) state of the sixth bit of register 5 is a sign of the presence (absence) of service information about the length or checksum of the array on register 6 of data. The linear (zero) state of the seventh bit of the register 5 corresponds to the operation of the device in the transmission (reception) mode. The single (zero) state of the first to fifth bits of register 5 corresponds to the presence (absence) and one of the five types of possible errors in the operation of the device:

checksum error (bit 1); end marker error (bit size 2); start marker error (bit 3); word reception time error (bit 4); error of waiting time for receiving a word (bit 5).

The data register 6 is intended for intermediate storage of data received from the communication channel to the recipient.

The 7-bit counter is designed to count the number of pulses arriving at input 49.1 of the device. A counter overflow signal is generated at its output upon reaching a state equal to eight, which corresponds to the number of bits in the data word.

The 8 byte counter is designed to record and store the current value of the length of the data array. After processing the next byte of data, the contents of counter 8 are decremented by one. The zero state of the counter 8 corresponds to the reception of the marker words of the data array.

The time counter 9 is designed to monitor the hangup of the communication channel when receiving a data array word.

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The time counter 10 is designed to monitor the hangup of the communication channel in pauses when receiving words, an array; data.

Triggers P and 2 are designed to register the reception of the marker words of the data array.

The trigger trigger 13 is intended to register the start of receiving the information part of the data array.

On the schemes of the algorithms (Figures 3-6), the following conditions are stated and abbreviated: RG - 1 register; P is the register bit; RI - spacer; elitel 15 pulses; max g is the limit value of the time counter;, T is the trigger; ST - counter; CTN - reading; CS - control amount; TCS - current control

amount; L is the length of the data array.

The device operates in two main modes: receiving data from a communication channel and transmitting data to a communication channel.

In the initial state, the registers 1-6 go to the input 49.1 of the device.

counters 7 and 8, counters 9 and 10 of time, triggers I1-13. are in the zero state (the initial installation circuit is not shown in Fig. 1).

The initial state of the device 30 corresponds to the mode of receiving data from the communication channel.

The zero and first bytes of the data array are the marker codograms (SSCR), which are used to quickly check the loop of the communication channel. The source device sends successively to the communication channel marker codograms. For each received marker codogram, the receiving device sends a acknowledgment codogram to the communication channel.

The source device controls the receipt of confirmation confirmation markers. Upon successful exchange of marker codograms, the source device sequentially transmits information to the receiver device in register 1. Register 1 is constructed according to a shift register scheme, with the shift operation being performed after writing the next information bit under the control of a synchronization pulse.

Upon receiving the first data bit, the synchronization pulse triggers the time counter 9, overwrites the time counter 10, increments the counter 7 state. For each received information bit, the described processes in the device flush until one of the two events occurs; counter overflow 7; overflow counter 9 time.

Overflow of counter 7 indicates that the reception of the byte of data from the communication channel has been completed. By the overflow signal of the counter 7, the counter 10 is started up, which monitors the delay time of the confirmation, and the count of the pause counter 42 is enabled. At the second synchronization input 49.2 of the device, the clock pulses are continuously generated in the communication channel and ensure the operation of the first 9 and second 10 time counters, the distributor 48 pulses and the pause counter 42. The frequency of the indicated sync pulses is K times the frequency of the synchronization, fasting

the math part of the data array. Moreover, for each transmitted byte of the data array, the receiving device forms a confirmation byte, which uses the received byte from the source device byte of the danc array. The source is at the end of the transmission of each byte of data, and the receiving device at the end of the reception of each byte is given8

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besides the initial markers, they form readiness signals causing interruptions in the work of their subscribers.

The source device provides time control for the receipt of acknowledgment bytes. In addition, the source device and the receiver device are responsible for calculating the checksum of the data array, which J is used to monitor; the quality of the exchange.

 Let us consider the implementation of the data reception mode from the communication channel by the example of marker codograms (Figs. 1 and 3).

The data on the communication channel is transmitted by successive codes, and the linear devices of the communication channels ensure the recovery of the information bit and the synchronization pulse. The information bit is fed to the input 48.1 of the device and under the control of the synchronization pulse, sweat

 stepping on input 49.1 devices.

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is written to register 1. Register 1 is constructed according to a shift register circuit, whereby the shift operation is performed after writing the next information bit under the control of a synchronization pulse.

Upon receipt of the first data bit, the synchronization pulse triggers the time counter 9, overloads the time counter 10, increments the state of the counter 7. For each received information bit, the described processes are flashing in the device until one of the two events occurs; counter overflow 7; overflow counter 9 time.

The overflow of the counter 7 indicates that the reception of the data byte from the communication channel has been completed. On the overflow signal of the counter 7, the time counter 10 is started up, which monitors the delay time of confirmation, and the counter of the pause counter 42 is enabled. At the second synchronization input 49.2 of the device, the clock pulses generated in the communication channel constantly operate and ensure the operation of the first 9 and second 10 time counters, the pulse distributor 48 and the pause counter 42. The frequency of the indicated clock pulses is K times the frequency of the synchronization pulses received during the reception of the codograms at the input 49.1 of the device (the coefficient K is conveniently chosen equal to 16)

The counter 42 under the influence of clock pulses changes its state from zero to three. The state of the counter 42, in addition to zero, corresponds to a sequence of three control signals generated at the outputs of the first control decoder 45 and providing a hard timing diagram of the device operation in the pauses between the received codograms. Under the influence of the control signals from the output of the decoder 45, the distributor 47 is started, and the received byte is rewritten from register 1 through multiplexer 36 into register 2. Then, the zero (initial) state of the register 1 and the counter 7 is set, the overflow signal at the output of which is removed, the counter 42 is set to the zero state, and its account is blocked.

If the first marker codogram is received on register 1, then at the output of element I-14, a single information i is formed which is written to the trigger H, if the marker codogram to the register 1 is received, then to one: the state is set to trigger 12,

After launching the distributor 47, a shift resolution signal and a series of shift synchronization pulses are input to its outputs, arriving at the corresponding inputs of register 2, as well as a series of pulses accompanying information transmitted to the communication channel, arriving at the output 52.1 of the device during transmission by a serial code codograms from register 2 to output 52.2 of the device.

In the event that the time counter 9 overflows, a reception error signal is generated in the device, which is recorded in the 4th digit of register 5. In this case, as in the case of any other error, a one-shot 46 is started via the OR 32 element. The one-shot 46 is reset by zeroing registers 1 and 3, counters 7 and 8, time counters 9 and 10, triggers 11-13, and through the OR 29 element, the output 54 of the device transmits an interrupt signal

The interrupt signal is processed by the subscriber, whereby the subscriber first reads the status word and register 5 through multiplexer 37, and then the state word analysis subroutines and the required sequence of interaction between the subscriber and the interface device are executed.

In the case that the first or second patterns received by the device are not marker (do not contain the -OCC code) in the device, an initial marker error signal is generated at the output of the AND 21 element, setting bit 3 of the register 5 to one,

After receiving two marker codograms, the device is ready to receive the information words of the data array.

The device operation algorithm when receiving an information word defining the length of the data array (Fig. 4) has the following distinctive features. The overflow signal of the counter 7 triggers the counter 42, and at the outputs of the decoder 45 single signals are generated, according to which the received information is copied from register 1 to counter 8 and into register b, bits Q and 6 of register 5 are set to one, on output 54 device through the element of the IPA 29 is issued an interrupt signal, and the trigger 13 is set to one state. Then, the triggers 11 and 12 are reset to the zero state. As with the reception of marker codograms, through multiplexer 36 from register 1 to register 2, the received bytes are copied, the distributor 47 is launched, the OR 28 element is used to set the device elements in readiness for receiving the next byte of data from the communication channel a communication channel from output 52.2 of the device transmits an acknowledgment codogram.

After receiving each consecutive data byte, a single signal is formed at the output of the element And 17. This signal records the byte received from register 1 to registers 2 and 6, writes the current checksum of data from the output of adder 41 to register 3, sets it to one bit About register 5, subtract a unit from the contents of counter 8 and send an interrupt signal to the subscriber. In addition, as before, the distributor 47 is started, through the OR element 28 the device is prepared to receive the next byte, and the communication channel from register 2 to sequence is in the one state of the seventh bit of register 5, the time counter 10 is started, all bits the register 2 is set to one (marker code) and the distributor 47 is started, organizing the transmission of the codogram from the output of the register 2 to the communication channel. Thus,

The code is transmitted and the byte is transmitted. The transmission of marker codograms is given.

ki On the interrupt signal, the subscriber reads the status word from register 5, determines the sign of the new information, reads the data from register 6, and zeroes the zero register register 5. The process of receiving data words continues until the counter 8 reaches a state equal to one, which determines receiving checksum data array. In this case, in the first code of the end-of-array decoder 44, a single signal is generated that blocks the recording of the current checksum of data from the adder's output. 41 into register 3, the recording of the checksum of the array from register 1 to register 4 is permitted and bit 6 of register 5 is set to one. The checksum byte, as well as the previous bytes of the data array, is transferred from register 1 to register 2. To transmit the confirmation byte, the distributor 47 is started, the interrupt signal is generated to the subscriber, and the decrement of the counter 8 is performed.

In the case of the HyjieBOM state of counter 8, the final marker coding is received. At the second output of the depragforator 44, a single signal level is established allowing., The comparison of the state of registers 3 and 4, the formation of a single signal level by. element output and 14 and

signals of a general reset of the device at 45 outlet 65 of the distributor with delay elements And 19 and 20, OR 27-31 at the end of the reception of the marker. The device is reset.

The features of the device in the transfer mode are as follows. The transfer of the device to the transmission mode (Fig. 6) and the data transmission control are carried out from the source subscriber. To do this, the address of the device is fed to the input 50, which is decoded by the decoder 39, and the signal to the input 51.2. When you first access the device, the settings are relative to the trigger signal,. necessary to record information in the transfer register 2, the content shift enable signal is generated

QQ register 2. At the outputs of the decoder 75 pulses are formed, corresponding to the states K / 2 and K (K is the maximum state) of the counter 73. These pulses arrive at the outputs

5g 52.1 and 64 distributors 47, respectively. The overflow signals of counter 73 produce the increment of counter 74, the overflow signal of counter 74, the corresponding window. The data for transmission goes to register 2 from input 48.2 through multiplexer 36 and is transmitted bit by bit to the communication channel under the control of distributor 47. After the transfer of any word, including markers, at the signal from the output 66, the distributor 47 through the element OR 28 to the output 54 of the device is given an interrupt signal. During data transfer

the device, in accordance with the accepted exchange discipline, receives acknowledgment bytes, performs time control of their timely

5 receipts and all other types of controls.

The operation of the device in the transfer mode ends upon receipt of acknowledgments to all transmitted

0 bytes, including the final marker, or when any of the five errors are fixed. In both cases, the zero state of the seventh bit of register 5 is set, the device general reset and interrupt signals are generated.

The operation of the distributor 47 (FIG. 2) starts from the moment it arrives at one of its start inputs (61 or

0 62) single signal. Wherein

A trigger 72 is set to one, permitting the operation of counters 73 and 74 from sync pulses coming from the input 49.2 of the device.

five

koi regarding the trigger signal,. necessary to record information in the transfer register 2, the content shift enable signal is generated

register 2. At the outputs of the decoder 75, pulses are formed, corresponding to the states K / 2 and K (K is the maximum state) of the counter 73. These pulses arrive at the outputs

52.1 and 64 distributors 47, respectively. According to the overflow signals of the counter 73, the increment of the counter 74 is produced. According to the overflow signal of the counter 74, the corresponding window 1314

In order to transfer the last bit of the codogram to the communication channel, a single pulse is generated at the output of the one-shot 76, which triggers 72 and counters 73 and 74 are set to the zero state. If there is a single signal at the input 63 of the distributor and, accordingly, . Allowing the subscriber to interrupt, the one-shot 76 impulse is post-passed through AND 78 to output 66 of the distributor 47.

Claims (1)

Invention Formula A device for interfacing a subscriber with a communication channel, containing a data register, a checksum register, two triggers, six AND elements, five OR elements, the output of the first trigger connected to the first input of the first element And, the output of the second trigger connected to the first input of the second element, .o tl and - so that, in order to increase the speed and reliability of data exchange, the device contains a receive register, transfer register, control register, status register, bit counter, byte counter, pause counter, two counter in , receive trigger, array end decoder, two multiplexers, three control decoders, a comparison unit, an adder, a delay element, a single-oscillator, a pulse distributor, seven AND elements, four OR elements, and the receive register information input and information register output of the transfer register the input and output of the device for connecting respectively to the information output and the input of the communication channel, the input of the record of the reception register is connected to the counting input of the bit counter, with the start input of the first time counter, The primary input of the first element OR is the input of the device for connecting the first synchronous output of the communication channel, the counting input of the 1 pause sensor is connected to the counting inputs of the first, second time counters, and the input of the device for connecting to the second synchronous module connection, the first synchronous output of the pulse distributor is the output of the device 14 for connecting to the synchronous input of the communication channel, the first group of information inputs of the first multiplexer - and the group of information outputs of the second multiplexer - form groups of inputs and outputs of the device for connecting - respectively to the groups of information outputs and 10 DON subscriber, control inputs The first and second control decoders are inputs to a device connected respectively to the first and second subscriber access outputs 15, a group of control inputs of the second multiplexer is connected to groups of information inputs of the first and second control decoders and connects a group of inputs to the device subscriber outputs, the output of the second element OR is the device output for connecting to the subscriber interrupt input, while 25 group of information outputs of the reception register is connected to a group of inputs of the third element And, with groups of information inputs of the byte counter, data register, register 30 checksum, with the second group of information inputs of the first multiplexer, with the first group of information inputs of the adder, the group of information outputs of which is connected to the group of information inputs of the control register, the group of information outputs of which is connected to the second group of information inputs of the adder and the first group -Q information inputs of the comparison unit, the output of which is connected to the first input of the fourth element I, the output of which is connected to the first input of the third element ICH- and g the first unitary state register input, the output group and the high-order output of which are connected to the first group of information inputs of the second multiplexer, the second 50 a group of information inputs of which is connected to a group of information outputs of a data register whose record input is connected to the first input of the second OR element, to the outputs of the fifth AND element and to the second single input of the state register, the high-level output of which is connected to the first inputs of tog-oh, the sixth element And, with grumbling 35 the input of the pulse distributor and the control input of the first multiplexer, the group of information outputs of which is connected to the group of information inputs of the transmission register, the enabling input and synchronous input of which are connected respectively to the enabling output and the second synchro output of the pulse distributor, the first starting input of which is connected to the installation input the transfer register, with the first start input of the second time counter4 with the third single input of the status register, with the first output of the first decoder control Alert, the second output of which is connected to the first input of the fourth element OR, the output of which is connected to the recording input of the transmission register and to the second trigger input of the pulse distributor, the third sync output of which is connected to the second input of the second OR element, the third input connected to the first zero input of the register state, with the installation j input byte counter, with the zero input of the receive trigger, with the output of the fifth ASR element, with the installation input of the control register, the recording input of which is connected to the output of the seventh el ment and having a first input coupled to the first output end of the decoder array and the first input of the eighth AND gate, a second input coupled to a second input of the seventh AND gate with. the first input of the sixth OR element, with the output of the ninth AND element, and the input of the delay element, the output of which is connected — the counting input of the byte counter, the output group of which is connected to the group of information inputs of the end-of-array decoder, the second output of which is connected to the first inputs of the ninth the tenth and eleventh And elements, with the input of the third And element, the output of which is connected to the information input of the first trigger, with the second inputs of the fourth, ten, eleventh And elements, with the first input of the twelfth stage Lemma And, p. the second input of the first element I, the output of which is connected to the information input of the second trigger, the synchronous input of which is connected to the first output of the third control decoder, with the second inputs In addition, the twelfth elements are And, with the third inputs of the fourth, eleventh And elements, with the synchronization of the first trigger, the zero input of which is connected to the zero input of the first trigger and the output of the seventh element OR, the first input of which is. go is connected to the first inputs of of the eighth OR element, with the second input of the first OR element and with the output of the one-shot, the start input of which is connected to the output of the third OR element, the second input of which is connected to the output of the second time counter and the fourth single input of the state register, the fifth single input of which is connected with the output of the first time counter and with the third | "input of the third element OR, the fourth input of which is connected to the output of the eleventh element AND, and with the sixth single input of the state register, the seventh single input of which is dinene with the fifth input of the third element OR and with the output of the twelfth element And, the third input of which is connected to the fourth inputs of the fourth, eleventh element And, with the first input of the thirteenth element And, with the output of the receive trigger, the second the input of which is connected to the second output of the third control decoder and to the second input of the second element AND whose output is connected to the record input of the byte counter, to the single input of the receive trigger, to the first input of the ninth element OR, and to the second input the sixth element OR, the output of which is connected to the second input of the fifth element AND, the installation input of the second time counter is connected to the output of the first the OR element, the third input of which is connected to the second input of the fifth OR element and the output of the tenth AND element, the third input of which is connected to the second input of the seventh OR element and the output of the thirteenth element AND, the second input of which is connected to the third output of the third control decoder and with the second input of the eighth element OR, the output which is connected to the installation input of the first time counter, to the installation input of the receive register and to the installation input of the bit counter, the overflow output of which connected to the second start input of the second time counter and the installation input of the pause counter, the first, the second outputs of which are connected respectively to the first, second information inputs of the third control decoder, the installation input of the status register connected to the first output of the second control decoder, the second output of which connected to the second and third are null The inputs of the state register, the eighth single input of which is connected to the input of the ninth element OR, the second input of which is connected to the output of the eighth element I and to the input of the checksum register record, the group of information outputs of which is connected to the second group of information inputs of the comparison unit, , the output of the sixth element AND is connected to the second input of the fourth element OR, C) ig.1 SL G. "7 f to I; -Yu LU ff6 1499358 C) g Reception marker H. odozf uMMki Receive one fuma daHHbif 8th & 1 ± ± I ffyfff account {ika9: drosschshchika10 at.stT f  CT7: 0 I )  . (. kana /} come out  Reset timer fj} OHa 3 L - Counts (L R & 5 (P $) 0 (spheres  interrupt) 1499358 ± shchika10 at.st f  CT7: 0 I / & f / Cr7 .- fZJ I Passing a marker to a comm link Cfpoc counter Have (ireryvalie) i ( The end) Fy G Nacha / u) f- -J npue / i kodo2rammy d / giil / | array of data) ( receiving one Sura 9anni) 1 9 t ± ± i Lusne snepchika9 C / foe sche / timsch GG7-C7 7n | I Jl + fft / cff u counter  KGB- KodL I R & 5 (P0, P6) n & 2: -HodL I start CT8-KodL I T1i.Tf2  counter 9  Interruption one C w) ± Th / TimGGG-C I Jl ± ff & 5 (P f) I Oifufuu cd / foc G jogging in (r5 (PS) i Ofufuu cfppc Interrupt ag five R beginning)   Transmission f- --- 1 9lkig | j fi-iy / 4. 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