SU1497616A1 - Programmable logic controller - Google Patents

Abstract

Use: in radio engineering. The goal is to increase speed. SUMMARY OF THE INVENTION: The controller comprises a program memory block, an address counter, an instruction register, a decoder, a clock generator, and a control unit. It additionally introduces a register of internal variables, a switch and a group of trunk transceivers. 1 il.

Description

3149

the main transceiver of the group (, M, where M is the size of the information input-output controller), the input-output of which is connected to the K-th input-output of the controller group, the output signs of the internal variable recording, the sign of the external variables and the direction of information exchange unit the controls are connected respectively to the synchronous input of the register of internal variables, the inputs for recording the output information and recording the indication of the operating mode of the main transceivers of the group, and the control unit contains two elements OR, two triggers, element NAND and eleven elements AND, the output of the first element OR connected to the output of the block command recording and the information input of the first trigger, the direct output of which is connected to the first inputs of the first and second elements AND, inverse Output of the first the trigger is connected to the first inputs of the third and fourth elements And, the input of the initial installation of the device is connected to the inputs of the installation in the field of the first and second triggers, the synchronous inputs of which are connected to the input of the clock pulses of the block, the third in the second element OR is connected to the output of the fifth element AND, the information input of the second trigger is connected to the output of the second element OR, the direct output of the second trigger is connected to the second inputs of the first and third elements AND, the inverse output of the second trigger is connected to the second inputs of the second and fourth elements And, the output of the first element And is connected to the output of writing the address of the block, the output

.

from 15 20 35 40

25

thirty

164

The second element And is connected to the first inputs of the fifth, sixth, seventh, eighth, ninth and tenth elements And, the second inputs of the fifth and tenth elements And are connected respectively to the input of the logical conditions of the block and the output of the element AND-NOT, the outputs of the ninth And the tenth elements And are connected respectively to the outputs of the signs of the skip of the next command and the transition to the next command of the block, the input of the command to write information of the block is connected to the third input of the And element, the second inputs of the sixth, seventh, eighth, ninth element And the first input of the NAND element, the second input of which is connected to the input of the logical conditions of the block, the third inputs of the NAND element of the sixth, seventh, eighth, ninth AND elements and the fourth input of the fifth AND element are connected to the input of the command attribute conditional transition and control of information transfer of the block; the block operation enable input is connected to the first input of the eleventh AND element, the second input and output of which are connected respectively to the output of the fourth AND element and the first input of the first OR element, the second inputs of the first and the second element OR is connected to the output of the third element AND; the input of the logical conditions of the block is connected to the fourth input of the ninth element AND, the outputs of the sixth, seventh and eighth elements AND are connected respectively to the output of the indication of the direction of information exchange of the block, the output of the recording of internal variables of the block and the output of the sign records of external variables of the block.

The invention relates to computing and discrete industrial automation and can be USED to build systems of logical control of technological objects in cases where the algorithms of functioning of the designed systems are formulated in the form of a log of logic algorithms (LSA), graph - schemes of algorithms, systems of Boolean functions and other forms of setting digital control automata.

The aim of the invention is to increase the speed and enhance the functionality by dynamically distributing the functions of the external outputs and introducing internal state variables.

Figure 1 shows the structural. programmable logic controller (11LK); figure 2 - structural diagram of the main transceiver group; in fig. 3 - scheme of the algorithm of the controller; on

51

Fig. 4 is a block diagram of a control unit; figure 5 - structural diagram of the switch

The PLC contains an address counter 1, a program memory block 2, a command register 3, a control block 4, a clock pulse generator B, a switch 6, an internal variable register 7, a decoder 8, a group of 9 main transceivers, inputs 10 and 11 of the initial setting and a permission indication controller operation, information input-output 12 of the controller.

Trunk transceiver of 15 or internal logical overexposure element And 13, trigger 14, three-stable element 15, element And 16, trigger 17, element And 18 and inputs 19-22.

depending on the values of these variables, the transition either at the same time to the execution of a command located in block 2 of the program memory directly after this command (if the value of the variable being checked is 1). either to PERFORMANCE

depending on the values of these variables, the transition either at the same time to the execution of a command located in block 2 of the program memory directly after this command (if the value of the variable being checked is 1). either to PERFORMANCE

the command whose address is specified in the address field (i.e. in the next word) the control unit contains the element AND 23, the element OR 24, the trigger 25, the output 26 of the block, the elements AND 27-34, the element OR 35, the trigger 36, the element AND 37, block output 38, element AND 39, command inlet (if the value of units 40 and 41 is checked, AND-NOT 42, mine is 0).

inputs 43 and 44 of the block, outputs 45-47 The format of the commands of the first type has a block. The following form.

word: code operational number input or internal

0-2 3 word: conditional address A,

О-п-1

it is variable. L: p-1

where A- and A are the addresses of the location of the command of the first group. 2. A group of commands for assigning values to logical variables, with which the values of 1 or O are made to an external output or internal logical variable. The format of the commands of the second type is: code of the output variable or internal variable

0-2 3 .00 p-2 p-1

3. A group of commands for specifying data transfer directions for individual external PLC outputs. The format of commands of this type is as follows: the code is the operation number of the external PLC output A.

0-2 3 ... p-1 The last group of commands is necessary to save the number of external PLC terminals implemented as single-chip LSIs, as well as for convenience

6

The switch contains a group of 48 elements H, an element OR 49, a group of .50 elements AND, inputs 51-53, a switch.

Block 2 of the PLC program memory is intended for storing the program for implementing the logic control algorithm represented by the PLC commands. The PLC command system consists of the following three types of commands.

1. A group of conditional jump commands that can be used to analyze the values of input variables and, at the same time, depending on the values of these variables, go to the execution of a command located in block 2 of the program memory directly after this command (if the value of the variable is 1). either to PERFORMANCE

the command whose address is specified in the address field (i.e. in the next word) of this command (if the value of the verification is 0).

input number or in

 3rd crossing A,

it is variable. L: p-1

build on the basis of these life span distributed multiprocessor SLN. ,

A complete system of commands is given in Table 1.

0 According to the selected command formats, the address space of the block 2 of the program memory of this 1 SC is 2, and the total number of input and output variables in the implemented

5 PLC logic control algorithms are bounded above by magnitude. The number of internal variables should also not exceed the value.

It can be seen from the tabLo that the write commands to different triggers of the PLC (the commands of the group M 2 and f} are distinguished by the first register bit of the 3 command register. The second bit of the 3 register register contains the value written to the selected

g i-th trigger variable

In the transition condition commands (commands of group no. 1 a |,), the second bit of the register of 3 commands determines by variable which source

0

a conditional transition will be performed: from register 7 of internal variables (at) or from switch 9 overlays (at).

In configuration commands (commands of group no. 3 3 1; a, 0), the second bit of register 3 of commands determines the direction of data transmission for the i-ro switch of 9 directions,

This command structure allows the execution of commands of group 2 to directly apply a trigger to the information input selected by the command. When executing the commands of the .V 1 group, the second register bit of the 3 commands directly controls the operation of the selector 6, which is removed from the output of the command being analyzed by the variable command.

All this allows us to simplify the structure of the control device 4 and reduce the number of control signals generated by it.

The control unit A provides for the implementation of PLC commands. The working time of the GShK is set by the generator of 5 pulses. The operation of the control unit is described by means of the firmware shown in FIG. According to this firmware, the control unit 4 implements the following micro-operations:

q) PA - to the register of 3 commands a word from block 2 of the program memory at the address containing in the counter 1 address;

q.) 27- write the contents of the second bit of the register of 3 commands to the trigger 14 of the output of the i-ro transceiver 9;

q ..) - the content of the counter i of the address is increased by, one;

q.) 1- record the contents of the second register register 3 commands in the i-th trigger register 7 internal variables;

q.) - the contents of counter 1 address is increased by two;

q,) 1 - record of the content of the second bit of the register of 3 commands to the trigger 17 of setting the i-ro transceiver 9;

q) PA: RK - the contents of the register of 3 commands are rewritten into the counter 1 address.

In addition, the following logic variables arrive at the input of the control device 4:

0

Q

P

five

P,) VC — if PI I, then the given PLC Bfii6paH and the logic control algorithm is executed, if P, 0, then the algorithm is not executed and all bidirectional outputs are in a state of high resistance;

P) —analysis of the value of the contents of the zero (senior) register register of 3 instructions;

RZ) PKfl - analysis of the value of the contents of the first register bit of 3 commands;

P) - analysis of the value of the variable V, which is in the i-th trigger of the register 7 internal variables (if RC) or in the input from the i-ro transceiver 9, if RC (2j 1.

The process of implementing logic control algorithms in a PLC can be divided into two steps: the preparation stage and the ethane of execution.

At the preparation stage, all the necessary transformations of the initial tasks of the algorithms are first performed. logical control in order to bring them to the internal representation of these algorithms adopted in the PLC, and then the converted algorithms are recorded in block 2 of the program memory. If we consider the specialized computer oriented to the solution of logic problems, that the preparation stage is the programming stage of this specialized computer. At the execution stage, the command implementation of the logic control algorithms written in block 2 of the PLC programs in the internal form of representation is carried out.

The correspondence between the input and output numbers of the control unit 4 and micro-operations is shown in Table 2. PLC works as follows. When switching on the PLC, it is necessary to supply a pulse signal to the input 10 Reset of the PLC, in addition to supplying the power supply voltage. The Reset signal transfers the PLC to the initial state indicated in FIG. For expanding an PLC, this means setting all triggers of the counter 1 address, register 3 commands, register 7 internal variables, triggers 14 and 17, transceivers of group 9 and triggers 36 and, 25 of control unit 4 to the zero state.

Then, a single potential is applied to the input II of the VK. At low level

at the input I1, the PLC is in the a state, and the bidirectional outputs are in the high resistance state. If, then the first command loaded in the zero cell of the program memory block 2, i.e. With. The command is loaded on the write strobe q, which is generated by control unit 4. -Three 26. The contents of the first two bits of register 3 of commands are analyzed in control unit 4.

If the contents of the zero bit of the register of 3 commands is zero (), then the current processing cycle will execute the command to write the contents of the second bit of the register of 3 commands to the i-th trigger of the 7 internal variables register or write to the trigger 14 of the i-ro transceiver 9. When the content value is the first bit of the register of 3 commands equal to O, control block 4 generates a write strobe q at output 47, which is fed to the record of all triggers of the internal variable register through AND-NOT elements. The second inputs of these elements are connected to the outputs of the decoder 8. Thus, the contents of RC C21 are recorded only in the 1st trigger of the register 7 internal variables, namely, the trigger whose address is specified in the command field from 3 to nl bit. -. Gate qj is output 45, which is fed to the input of incrementing the contents of counter 1 address by one. When the value of the contents of the first bit of the register of 3 commands equals 1, the control unit 4 generates a write strobe q at output 20, which is fed to the first input of the AND 13 element of all transceivers in group 5 of input 11 RV three-staged buffers 15

9. The second inputs of the AND 13 co-all PLC elements go to the state: merged with the outputs of the decoder 8, which resistance, i.e. PLC off gate strobe q goes to sync from bus to which it connects trigger 14 of that transceiver to terminals 12. Simultaneously from the switch whose address is specified in the strobe field of recording strobe q unit 4 of control 3 commands 3 to n The -1 bit of the output generates a strobe; the second commander's register 3 is input to the increment input and goes directly to the address information register 1 per unit, the trigger trigger input 14. In this case

55

if trigger 17 is in state 1, then element AND 16 is open, since at the input 11 of the VC it is also 1, and therefore, the three-stable buffer 15 is open. Therefore, the value of RK 2,

If the contents of the zero and first bits of the register of 3 commands are equal to one f ff, then the conditional branch command will be executed in the current processing cycle. By doing

recorded in the trigger 14 i-ro receiver, transmitter 9, also on the output 12 of this transceiver. Simultaneously with the generation of the recording strobe q}, the control unit 4 generates a strobe q arriving at the input of incrementing the contents of the counter I of the address by one.

0 If the contents of the zero bit of the register of the 3 commands are equal to one (P 1), and the contents of the first bit of the same register are zero (), then in the current processing cycle there will be

5 execute the i-ro tuning command of the transceiver 9 for the input mode or for the output mode. Block 4 The NIN control generates a recording strobe q on the output 21, which goes to

About the first input of the And 18 element of all transceivers of the group The second inputs of the And 18 elements are connected to the outputs of the decoder B, therefore the strobe q / arrives at the synchronous input 17 of the transmitter's 5 receiving address specified

in field 3 through p-1, the register bit of 3 commands o The output of the trigger 17 through the element 16 is connected to the control input of the three-stable buffer 15. I

0 At the same time, if the RC 2j 1, then the unit 17 is recorded in the trigger 17, and this transceiver is focused on the Toe information. Bidirectional output is represented as the output to which control signals are received. If RK 2 0, then zero is recorded in the trigger 17 and this transceiver is oriented to receive information, the three-stable buffer is 15

0 is in a high impedance state and the bidirectional output is represented as an input, which receives information signals from the outside. If there is zero potential on

If the contents of the zero and first bits of the register of 3 commands are equal to one f ff, then the conditional branch command will be executed in the current processing cycle. By doing

conditional jump commands also analyze the value of a variable. The address of the device from which the variable is received is specified in bits 3 through n-1 of the register of 3 commands, as well as in RC 2. If PK 2 0, then is the variable stored in the iM trigger register of internal variables 7, o If the RC, then Vfi is the output value of the i-th transceiver of group 9. Depending on the setting of this transceiver, is either the value of the external input variable arriving at input 12, or the value of the output trigger of the i-ro transceiver.

If the variable to be analyzed is, then in the address counter 1 the address of the next command is generated, which is located through one cell of the memory 2 of the program relative to the current command. In this case, the control unit 4 generates a strobe to the gate 46,

eleven

ten

0 1

 ten

0 0

R F

 0

100

according to which the counter 1 address is incremented by two. If, however, the variable Vti 0 is being analyzed, then in the next processing cycle the command will be executed, the address that is written in the program next to the current command cell of memory 2 To write to the counter 1 the address of the command to which the transition is made, you must perform three successively microinstructions First, control unit 4 generates a strobe q, by which the contents of address 1 are incremented by one, then the next clock impulse produces strobe q to write into the register of 3 commands selected from block 2 of program memory at the address located in counter 1 addresses, addresses of transition. And further on, a new clock pulse to output 38 produces a recording gate strobe q, according to which the contents of register 3 of commands are copied to counter 1 of the address,

Table 1

The conditional transition by the value of the external m input variable The conditional transition by the value of the internal variable Assignment of value 1 of the i-th internal variable Assignment of value

0i-th internal variable Assignment of value

1i-th external output variable Assignment of value About i-th external output variable Setting the output direction of data transfer for i-ro switch Setting the input direction of data transfer for 1st switch

Yu

r

table 2

It

I (pl jf, |

0

/, "

tt

Editor A.Lszhnina Tehred M.Hodanich

Order 4445/49 Circulation 668 Subscription

VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5

Production and publishing plant Patent, Uzhgorod, st. Gagarin, 101

uh

M

J)

and

) t

"

IF

Eh

JO

M

"L-j

40 fO

four}

U (.5

Proofreader T. Kolb

Claims (1)

A PROGRAMMABLE LOGIC CONTROLLER containing a program memory block, an address counter, a command register, a decoder, a clock generator and a control unit, the output of the address part of the command register commands being connected to the decoder input and the information counter input, the output of which is connected to the address input of the memory block programs, the output of which is connected to the information input of the command register, the sync input of which is connected to the output of the command record of the control unit, the outputs of the first and second senior bits to Yes, the operations of the command register are connected respectively to the inputs of the sign of the commands for recording information and the sign of the commands of the conditional transition and control the transmission of information of the control unit, the output of the clock 'pulses generator is connected to the input of the clock pulses of the control unit, the reset input and the enable input of which are connected respectively to the input of the initial setting the controller and the input of the sign of permission of the controller, the outputs of the signs of the transition to the next command, skipping the next command and writing the address of the block the equations are connected respectively to the input of adding one, the input of adding two, and the synchro input of the address counter, characterized in that, in order to improve performance, the register of internal variables, the switch and the group of trunk transceivers are entered into it, by which the input of the initial setting to zero of the instruction register, the register of internal variables and inputs of the initial installation g of trunk transceivers of the group, the input of the sign of permission of the controller is connected to the inputs of the sign of permission of the Output mode and formations of the trunk transceivers of the group, the outputs of which are combined and connected to the first information input of the switch, the second information input and output of which are connected respectively to the output of the register of internal variables and the input of the logical conditions of the control unit, the output of the decoder and the low-order output of the operation register code of the command register is connected to the control input switch, the low-order output of the operation code of the instruction register is connected to the information input of the register of internal variables and to the input inputs of the group transceivers, the Kth output of the decoder is connected to the write enable input to the Kth bit of the register of internal variables and the sampling input of the Kth SU 1497616 A1 of the trunk transceiver of the group (K = 1, M, where M is the bit depth of the controller's information input-output), the input-output of which is connected to the K-th $ input-output of the controller group, outputs of signs of recording an internal variable, sign of writing external variables and the sign of the direction of information exchange of the control unit are con- nected | Q to the sync input of the register of internal variables, inputs of the record of the output information, and the record of the sign of the operating mode of the main: group transceivers, 15 and the unit is controlled It contains two OR elements, two triggers, an AND element and eleven AND elements, the output of the first OR element being connected to the output of the command record of block 20 and to the information input of the first trigger, the direct output of which is connected to the first inputs of the first and second AND elements, inverse per25 Vågå output connected to the first latch ¹ vho- give third and fourth aND gates' input initial setting device is connected to the inputs of the installation in the first and second flip-flops, which are connected to the clock input 30 clock pulses bl ka, the third input of the second OR element is connected to the output of the fifth AND element, the information input of the second trigger is connected to the output of the second OR element, direct 35 the output of the second trigger is connected to the second inputs of the first and third elements AND, the inverse output of the second trigger is connected to the second inputs of the second and the fourth element And, 40 the output of the first element And is connected to the output of the recording address of the block, the output of the second element And is connected to the first inputs of the fifth, sixth, seventh, eighth, ninth and tenth elements And, the second inputs of the fifth and of the tenth elements AND are connected respectively to the input of the logical conditions of the block and the output of the element AND NOT, the outputs of the ninth and tenth elements AND are connected respectively to the outputs of the signs of skipping the next command and switching to the next command of the block, the input of the sign of the command to write information of the block is connected to the third input of the fifth element And, the second inputs of the sixth, seventh, eighth, ninth elements of the AND components and the first input of the AND element, the second input of which is connected to the input of the logical conditions of the block, the third inputs of the AND element, the sixth oh, the seventh, eighth, ninth elements And and the fourth input of the fifth element And are connected to the input of the sign of the conditional transition commands and control the transmission of information of the block, the input for enabling the block is connected to the first input of the eleventh element And, the second input and output of which are connected respectively to the output of the fourth AND element and the first input of the first OR element, the second inputs of the first and second OR elements are connected to the output of the third AND element, the input of the logical conditions of the block is connected to the fourth input of the ninth element And, the outputs of the sixth, seventh and eighth elements And are connected respectively to the output of the sign of the direction of exchange of information of the block, the output of the sign of recording internal variables of the block and the output of the sign of recording external variables of the block.