SU1488837A1 - Unit for sliding spectral-correlation analysis - Google Patents

Description

The invention relates to computing and can be used in devices for calculating the correlation functions of deterministic and random processes, as well as in digital correlation filtering devices. The purpose of the invention is the expansion of the class of tasks

by calculating the correlation

functions. The device contains two analog-digital converters 1, 2, block-3 direct theoretical-numerical spectral conversion and blocks 4, 5 of the inverse number-theoretic temporal conversion, each of which contains an adder, nodes 7, 8 of memory, registers 9-12, adder 13 modulo Fermat numbers, a multiplier for the number two in a positive integer degree (blocks 4, 5 contain multipliers for the number two in a negative integer degree), result registers 15, 16, a multiplier 17 and a synchronizer 18. The device is based on the analytical result, allowing to calculate the correlation function in the "sliding window" on the values of the instantaneous spectra of the input signals.

1 il.

with

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3

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The invention relates to the field of computing and can be used in devices for calculating the correlation functions of deterministic and random processes, as well as in digital correlation filtering devices.

The purpose of the invention is the extension of the class of tasks by calculating the correlation function.

The calculation of the correlation functions using theoretical-numerical transformations (PTS) is based on the following.

If and £ y (n) ^ are sequences of real numbers and their correlation function is determined by the relation

ζ (η) = X - x (n) y (n + m), (1)

N t ± go

then 5 * = Τ4Π {ζ (η)} = FTHP [y (n)] x

* OTCHP [x (p) ^, (2)

where PTSHP and OTCHP - direct spectral and inverse time theory and number transformations;

= I έ ^ζ ( ^η ) '^ ^ηΚ , (3)

n = o

The procedure for calculating the correlation function by transferring computations from the time domain to the frequency domain by expression (1) is thus reduced to calculating the pointwise products of UTPP ίχ (η)} and PTS {y (n)} ·

The drawing shows a block diagram of the device.

The device contains the first and second analog-to-digital converters (ADC) 1 and 2, block 3 PTSCHP, the first and second blocks 4 and 5 OTCHVP, each of which contains the adder 6, the first and second nodes 7 and 8 of the memory, first, second, the third and fourth registers 9–12, the adder 13 modulo the Fermat number, the multiplier 14 by the number two in a positive integer (the first and second blocks 4 and 5 of the PELVS contain a multiplier by the number two in the negative integer), the registers 15 and 16 of the result , multiplier 17, synchronizer 18.

The device works as follows. '

The synchronizer 18 generates pulses so that the change of information in the first and second ADCs 1 and 2, the first block 7, registers 9, 15 and 16 occurs K less often than in other blocks, where K is the number of calculated coefficients.

The numbers to be processed in the device are given as integers modulo where = 2, + 1. The number of memory cells is N = ζ, the bit width b = 2 *.

With the input to the information input of the ADC 1, the values of the function y (n) and the signal "Start C" to the start inputs of the ADC 1 and synchronizer 18 generate the signals necessary to synchronize the operation of the device. Each pulse from the fourth output of the synchronizer records the increment of the reference y (n) - y (p – D) into the first register 9, the first node 7 of the memory records the value of the reference y (n) and the output value y appears on its output (p –P +1) = A. The first ADC 1 generates a new reference code y (n + 1) = B and supplies it to the first input of the adder 6 and to the input of the first memory node 7. The second input of the adder 6 from the output of the first memory node 7 is supplied with the value A. The adder 6 performs the subtraction -: В ~ А and the result is fed to the information input of the first register 9. In this condition, the first ADC 1, the adder 6, the first memory node 7 and The first register 9 remains until the next pulse arrives from the fourth output of the synchronizer 18, which writes the next difference to the first. register 9 and the sequence of operations is repeated.

The output of the first register 9 is fed to the first input of the adder 13 modulo the integer Fermat number, the second input of which is fed sequentially from the output of the second memory node 8 through the second register 10 values 3 ^ (n-1) coefficients stored in the second memory node 8. The resulting sum [^ 5 * (η-ί) + (y (n) - y (pC)) 3 should be multiplied by 2 ^k , where K is the number of the harmonic under study. Numbers are generated in each cycle at the third output of the synchronizer.

Multiplication by 2 ^{K is} performed by loading the data into the double register

lengths starting with a register high

orders filled with zeros of the register

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low orders, shifting the contents of the double-length register to the left and subtracting the contents of the high-order register modulo the whole Fermat number from the low-order register. The operation of shift and subtraction in the multiplier 14 by the number two is in a positive integer degree synchronized by pulses from the second output of the synchronizer 18.

Similarly, the function of the second ADC 2 and the first block 4 OTCHVP. A distinctive feature of both the first block 4 OTSP and the second block 5 OTFC is the replacement of multiplications by 2 multiplications by 2 ~, which corresponds to a change in the direction of shift of numbers in the multiplier 14.

Thus, during one / sampling period, a full cycle of exchanging numbers in the second node 8 of the operational memory occurs, i.e. formed by the new values of the coefficient—

Comrade 5 ^ and, respectively, for block 25 with the input of the second memory node, output

3 PTSHP and the first unit 4 OTCHVP. The values of these coefficients, calculated at the last step of each sampling period, are entered into result registers 15 and 16, respectively. from the outputs of which they arrive at multiplier 17, where they are multiplied; the output of the multiplier 17 is connected to the information input of the second block 5 of the TORP, which operates similarly to the first unit 4 of the PSTVP. At the output of the second block 5 OTSP, N values of the correlation function are formed during each sampling period.

For each next pair of input samples, y (n) and x (n), the calculation process is repeated.

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Claims (1)

Claim A moving spectral correlation analysis device containing the first analog-to-digital converter, a direct theoretical-numerical spectral conversion unit and a synchronizer, the unit of the theoretical-numeric spectral conversion contains an adder, first, second, third, fourth registers, first and second memory nodes, modulo Fermat and multiplier by the number two in a positive integer, the information input of the analog-digital converter is the first information input of the device in the direct theoretician — numbers — 5 second spectral conversion information input of the first memory node and the first input of the adder are connected by the output of the first analog-digital converter, the second input of the sum of 10 tori is connected to the output of the first memory block, the output of the adder is connected to the information input of the first register, the output of which is connected to the first input of the modulo adder The 15th number of Fermat, the second input and output of which are connected respectively to the output of the second register and the information input of the third register, the output of which is connected to the information input ode multiplier by the number two to a positive integer, the output of which is connected to the information input of the fourth register, the output of which is connected to the information 40 45 50 which is connected to the information input of the second register, the clock input of the multiplier by the number two is in a positive integer degree connected to the 30th first output of the synchronizer, the synchronizing input of the multiplier to the number two is in the positive integer degree connected to the clock inputs of the second, third, fourth registers, the second memory node and the second output of the synchronizer, the clock input of the multiplier by the number two is positively connected to the third output of the synchronizer, the clock inputs of the first register and the first memory node connected to the fourth output of the synchronizer and the clock input of the first analog-to-digital converter, the synchronizer start input is connected to the start input of the analog-digital converter and is the device start input, the synchronizer stop input is the device stop input, characterized in that due to the calculation of the correlation function, the second analog-digital converter, the first and second result registers, the multiplier and two blocks of the inverse theorem are introduced into it Iko-numerical time transformation ¹ , each of which contains an adder and two memory nodes, four pe7 1488837 eight a gistra, an adder modulo the Fermat number, and a multiplier by the number two to a negative integer degree; in the first block of the inverse time-theoretic transformation, the information input of the first memory node and the first input of the adder are connected to the output of the second analog-digital converter , the output of the fourth register is connected to the information input of the first register of the result; in the second block of the inverse number-theoretic transformation of information, the input of the first memory node and the first input of the first adder are soy dinene with the output of the multiplier, the output of the fourth register is the output of the device, in the first and second blocks of the inverse time-theoretic transformation, the second input of the adder is connected to the output of the first memory node, the output of the adder is connected to the information input of the first register, the output of which is connected to the first the adder modulo Fermat number, the second input and output of which are connected respectively to the output of the second register and the information input of the third register, the output of which is connected to the · multiplier by The number two in negative integer power, the output of which is connected to the data input of the fourth register, the output of which connected to the information input of the second memory node, the output of which connected to the information input of the second register, the clock input of the multiplier by the number two to a negative integer degree is connected to the first output of the synchronizer; the synchronizing input of the multiplier to the number two to the negative integer degree is connected to the clock inputs of the second, third, fourth registers, the second memory node and the second output synchronizer, the clock input of the multiplier by the number two is negatively connected to the third. to the third output of the synchronizer, the clock inputs of the first register and the first memory node are connected with the fourth output of the synchronizer, the output of the fourth register of the direct theoretical and numerical spectral conversion unit is connected to the information input of the second result register, the clock input of which is connected to the clock input of the first result register and the fourth synchronizer output, the outputs of the first and second result registers are connected to the corresponding inputs of the multiplier, information the input of the second analog-to-digital converter is the second information input of the device, the start input and clock the input of the second analog-to-digital converter is connected, respectively, to the device start input and the fourth synchronizer output.