SU1481882A1 - Displacement-to-code converter - Google Patents

Abstract

The invention relates to a measurement technique, namely, means for measuring displacements using discrete sensors based on periodic structures. The aim of the invention is to improve the reliability of recording failures, expanding the scope and simplifying the converter. To do this, the movement converter has a code containing a movement sensor 1, shapers 2 and 3 pulses, elements 4 and 5 of memory, a generator of 6 pulses, elements AND-NOT 12 and 14, and a reversible counter 16, entered elements AND-OR-NOT 7 and 8, the elements EXCLUSIVE OR 9-11, the element OR-NOT 13 and the element NOT 15. The goal is achieved due to the fact that as a result of the introduction of the elements EXCLUSIVE OR 9-11 and the elements AND-OR-NOT 7 and 8, the structure of and expanded capabilities for processing the signals of displacement sensor 1, which allowed additional It is possible to receive information about faults in the displacement sensor 1. 3 il.

Description

one

The invention relates to a measurement technique, in particular, to means of measuring displacements using discrete sensors constructed on the basis of periodic structures.

The purpose of the invention is to improve the reliability of the registration of failures, expanding the scope and simplification of the converter, jQ

Figure 1 shows the electrical circuit of the displacement transducer to the code; Fig. 2 shows signal timing diagrams explaining the operation of the converter while maintaining the accuracy of 15 information; on fig.Z - the same, with the loss of reliability of information and registration of a collection of |

The displacement transducer to the code contains displacement transducer 1, forwarders 2 and 3 impulses, elements 4 and 5 of memory, generator of 6 impulses, elements AND-OR-NOT 7 and 8, elements EXCLUSIVE OR 9-P, element AND-NOT 12, element 13, element 25 AND-NOT 14, element 15, reversible counter 16.

The converter works as follows.

14818822

Figs, 2 and 3 (pos. Block). The output signals of the memory element 4 (FIG. 2A, B) are slightly offset relative to the original signals.

(FIG. 2 A, B), with the edges of the signals moving apart for the duration of the blocking pulse. This ensures a clear separation of the counting pulses even if, due to imperfect sensor 1, the interval between the fronts will be less than two pulse periods of the clock generator 6.

If, as a result of the imperfections of the input signals, three consecutive edges belonging to different outputs of sensor 1 (Fig. 3) are brought closer, then the blocking of two signals from the outputs of sensor 1 lies on each other and the counting direction cannot be recognized. In this case, however, a signal appears Failure at the output of the OR-NOT 12 element, which is detected by a visual alarm device and warns the user about the loss of information.

Each counting pulse corresponds to a signal on one of the Element 1 when moving a 30 TOTAL OR 10 or 11,

The link produces two sequences of periodic signals that are nominally 90 ° out of phase. These signals, passage through shapers 2 and 3 pulses, are synchronized by pulse generator 6 and recorded in memory element 4 on the leading edge of a clock pulse (Fig. 2 A, B, C) "In the second memory element 5 this information will be rewritten on the front the front of the next clock pulse, over one period of the clock generator 6 at the inputs of the element EXCLUSIVE OR 10 there will be different information that will cause a signal at its output, This signal, having passed through the element OR-NOT 13, on the element AND-NOT 14 will block the passage clocking pulses to the clock input of the memory element 4, and the output state of this element 4 will not change even if new information comes to the inputs of the memory element 4, the State where the memory element 4 does not perceive the input information, called lock. The timing diagram of the occurrence of locks is shown in

five

0

five

0

five

counting is determined by element 9, which marks the coincidence or discrepancy of the state of memory element 5, the output signals of element 5 control on the AND-OR-NOT 7 and 8 elements the passage of pulses +1 or -1,

Claims (1)

Invention Formula A motion converter in a code comprising a motion sensor, the first and second outputs of which are connected through a corresponding pulse shaper to the first and second information inputs of the first memory element, the first and second outputs of which are connected to the corresponding information inputs of the second memory element, the pulse generator, the first and the second element IS-NOT, the output of the second element IS-NOT is the control output of the converter, the reversible counter, the outputs of which are information outputs of the converter brazovatel, characterized by the fact that, in order to increase the reliability of registration of failures, to expand the scope of application and simplify 314 element, NOT element, three elements EXCLUSIVE OR, element OR-NOT and two elements AND-OR-NOT, the output of the pulse generator is connected to the first input of the first element AND-NOT and through the element NOT to the recording input of the second memory element, the output of the first element is NOT connected to the input. Recording of the first memory element whose outputs are connected to the first inputs of the first and second elements EXCLUSIVE OR, the outputs of the second memory element are connected to the second inputs of the first and second elements EXCLUSIVE OR and to the inputs of the third ele COPE EXCLUSIVE OR the output of the first element EXCLUSIVE OR is connected to the first inputs of the first elements AND the first and second elements AND-OR-NOT and the first inputs with lAJTJTJTJlJTJTJl 24 the second element AND-NOT and the element OR-NOT, the output of the second element EXCLUSIVE OR is connected to the first inputs of the second element AND the first and second elements AND-OR-NOT and the second inputs of the second element AND-NOT and the element OR-NOT, direct output of the third EXCLUSIVE OR CONNECTED with the second inputs of the first element AND the first element AND-OR-NOT and the second element AND the second element AND-OR-NOT, and the inverse output - with the second inputs of the second element AND the first element AND-OR-NOT and the first element AND the second element AND-OR-NOT, the outputs of the AND-OR-elements are NOT connected with respectively. The counter-volume inputs of the reversible counter, the output of the element OR NOT, is connected to the second input of the first element NAND. FIG. 2