SU1478296A1 - Multi-channel recursive filter - Google Patents

Abstract

The invention relates to radio engineering and can be used to filter signals coming through independent channels. The purpose of the invention is to improve the accuracy of filtration. The filter contains seven switches 1, 11, 20, 13, 10, 18, 16, synchronization unit 2, two adders 3, 19, five groups of N multipliers 8, 9, 14, 15, 17. The goal is achieved by introducing the distributor 4 signals, two switches 7, 12, L blocks of two series-connected delay elements 5, 6 and their connections with other elements, thereby reducing the mutual influence between channels without increasing the speed requirements of delay lines by distributing the stream of samples to be time shift across multiple delay lines and. 4 il.

Description

1

The invention relates to Oak radio engineering and can be used to filter signals coming in from N independent channels.

The purpose of the invention is to improve the accuracy of filtration.

Figure 1 shows a structural electrical circuit of a multi-channel recursive filter; Figure 2 shows the synchronization block circuit; FIGS. 3 and 4 are timing diagrams explaining their work.

The multichannel recursive filter (Fig. 1) contains the first switch 1, the synchronization unit 2, the first adder 3, the distributor of 4 signals, the 1 + 1 group consisting of the first and second elements 5-1 - 5- (1 + 1) and 6- 1 - 6- (1 + 1) delay, the eighth switch 7, the first group of i-C N multipliers 8-1 - 8-H, the second group of N multipliers 9-1 - the fifth switch 10, the second switch 11 , ninth switch 12, fourth mountain switch 13, third group of N multipliers 14-1 to 14-N, fourth group of N multipliers 15-1 to 15-N, seventh switch 16, fifth group of N multipliers 17 -1 - 17-N, sixth to switch 18, the second adder 19, the third switch 20.

The synchronization unit 2 (FIG. 2) contains a clock pulse generator 21, pulses 22 and 23 pulses, a pulse frequency divider 24, an inverter 25.

Multichannel recursive filter works as follows.

The output analog signals input to the first switch 1 are converted by it into a time-compacted sample sequence with a sampling period of the signal of one channel equal to Td (Fig. 3 and 4a, in this example, N 2). The sampling frequency at the input of the first adder 3 is 2 Td (with N channels) and equal to the information shift in the elements 5-1 - 5-N and 6-1 - 6-N delays. The signal distributor 4 operates in such a way that at each of its outputs a sequence of signal samples is formed, separated by protective positions, with 1 protective positions located between adjacent readings. The signals at the outputs of the distributor 4 are shown in FIG. 46, in for the case of 1 1 and-in fig.4g, d, e for I 2 (for the purpose of simplification, the amplitudes of all the samples are shown equal). Similarly, the output signals of the distributor 4 are generated at any value of 1. In the 5-1 to 5-N and 6-1 to 6-H delay elements, each of which has a delay of N ticks, both protective and full ones are entered. temporary positions. Mutual effects between the time channels are most pronounced at closely spaced time positions, therefore, the introduction of protective gaps such effects weakens. At the same time, the magnitude of the displacement of the poles of the transfer functions of the channel filters is reduced, distorting their design characteristics. At the same time, from the time diagrams of Fig. 4a-e, it can be seen that the introduction of any number 1 (both less and more N) protective positions due to the distribution of the output stream of samples of the first adder 3 over (1 + 1) -th groups of elements 5 -1 to 5-N and 6-1 to 6-N delays are achieved without increasing the sample shift frequency in them, which remains equal to MTd. Combining their output signals in the eighth and ninth switches 7 and 12 restores the time structure of the compressed sample stream corresponding to FIG. 4a, so all the switches and multipliers operate in the same mode as in the absence of protective positions. Since each of the elements 5-1 - 5-N and 6-1 - 6-N delay provides a shift of the sample flow by N intervals T, then at any time position at the outputs of the first adder 3 and the eighth and ninth switches 7 and are counts of signals of the same channel. At the same time, the fifth, second, t fourth, seventh and sixth switches 10, 11, 13, 16 and 18 connect those multipliers of the first, second, third, fourth and fifth groups of 8-1 to 8-N, 9-1 to 9 -N, 14-1 through 14-N, 15-1 through 15-N and 17-1 through 17-N, which determine the weighting coefficients of the transfer function in a given channel.

The filtered signals of each channel are extracted by the third switch 20 in the form of N reference sequences. To separate the channel signals in analog form, each output of the third switch 20 must include a low-pass filter.

with frequency cutoff frequency response 1/2 T.1. The clock signals necessary for the operation of the circuit are formed in synchronization block 2, which can be constructed, as shown in FIG. 2, on the basis of NTD frequency generator 21, frequency divider 24 into two, inverter 25, two counters 22 and 23 each of which cyclically calculates N and 1 Pulses of frequency NT1, respectively

BUT

(The signals at the second output of the synchronization unit 2 correspond to the case of using as delays 5-1 to 5-N and 6-1 to 6-N delays of two-phase devices with charge coupling).

Claims (1)

Invention Formula A multi-channel recursive filter containing a series-connected first switch, the N inputs of which are the inputs of a multi-channel recursive filter, and a first adder, the second switch connected in series, a second adder, and a third switch, whose N outputs are outputs of a multi-channel recursive filter, fourth and n commutators, the outputs of which are connected respectively to the second and third inputs of the first adder, the first group of N multipliers whose inputs are combined, and the outputs connect with the corresponding signal inputs of the nth switch, the second group of N multipliers, whose inputs are connected to the output of the first adder, and the outputs are connected to the corresponding signal inputs of the second switch, the sixth and seventh switches, the outputs of which are connected respectively to the second and third inputs of the second adder, the third group of N multipliers whose inputs are combined and connected to the inputs the first group of N multipliers, and the outputs are connected to the corresponding signal inputs of the seventh switch, the fourth and fifth group of N multipliers, whose inputs are combined, and the outputs are connected to the corresponding signal inputs of the fourth and sixth switches, respectively, the first group of the first connected and the second delay elements, as well as the synchronization unit, the first output of which is connected to the control inputs of the first, second, third, fourth, fifth, sixth and seventh switches, and The second output is connected to the control inputs of the first and second delay elements of the first group, characterized in that, in order to increase the filtration accuracy, 1 groups of the series-connected first and second delay elements are introduced, the control inputs of which are connected to the second output synchronization unit, signal distributor, the signal input of which is connected to the output of the first adder, and the outputs are connected to the inputs of the first group delay elements, the eighth switch, the signal inputs of which are connected to the outputs the first delay elements of the respective groups, and the output is connected to the combined inputs of the first group of N multipliers, as well as the ninth switch, the signal inputs are connected to the outputs of the second delay elements of the corresponding groups, the output is connected to the combined inputs of the fourth and fifth groups of N multipliers, and the control input of the ninth switch, the control inputs of the eighth switch and the signal distributor are connected to the third output of the synchronization unit.