SU1478224A1 - Device for multiaccess channel simulation - Google Patents

Abstract

The invention relates to computing and can be used in modeling computer I / O channels. The aim of the invention is to enhance the functionality of the device by determining the probability values of the channel capacity. The goal is achieved by introducing adder 4, group 3 of switches and group 8 random number generators with a variable upper limit of the generated sequence into the device. The simulation results are accumulated in a counting block 12. 1 Il.

Description

one

The invention relates to computing and can be used in modeling computer I / O channels.

The aim of the invention is to expand the functionality of the device by determining the probabilistic values of the channel capacity.

The drawing shows a functional diagram of the proposed device.

The device contains a generator of 1 clock pulses, a generator of 2 message pulses, a group of switches 3, an adder 4, first 5, second 6 and third 7 decoders, group 8 random number generators, first 9, second 10 and third 11 counters, counting , block 12 and block 13 decryption

The device works as follows.

Messages from generator 2, synchronized by generator 1, do

At the inputs of all switches, three groups are controlled by separate generators of 8 random numbers. Each of the switches 3 is a demultiplex.

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5 is activated by output only if there is a unitary code at its input, thereby simulating the situation,,. when one message passed through the channel without overlapping. The decoder 6 i is triggered when there is a combination of the type all zeros at its input, to simulate the process of having an empty clock in the channel. Code combinations at the output of adder 4 containing more than one 1 trigger the decoder 7, which simulates a message overlay situation. Signals from output 15 of decryption unit 13 are counted in counting unit 12, the number of processed messages accumulating on counter 9, the number of empty ticks on counter 10, and the number of unsent transmitted messages on counter 11. The likelihood P of successful transmission of a message over the channel is determined as follows:

20

M1 / (M1

M2, MZ

M2 h-MZ)

accordingly, the counters are 9-11.

type one litter in M, where M is the number of switch outputs. Thus, the code received from the random number generator 8 to the control input of the switch determines the number of the switch output on which the message appears from its input. If the random number at the control input of switch 3 does not fall within the interval (1 ... M), then the message does not pass through the switch.

Thus, by adjusting the upper limit of the generated random number generator sequences 8, you can change the intensity of messages in the channel, and you can set your upper limit for each random number generator 8. Adder 4 performs the role of a multiple random access channel. At the output of the adder 4, the sum of all messages simulated by the pulse signals is received in each clock cycle. The maximum value at the output of the adder 4 is equal to the number of its inputs.

Information from the output of the adder 4 in a parallel code enters the decryption unit 13. In this case, the decoder

Claims (1)

Invention Formula A device for simulating a multiple access channel, comprising a clock pulse generator, a message pulse generator, a decryption unit and a counting unit, the output of the decryption unit being connected to the input of the counting unit, characterized in that, in order to extend the functionality by determining the probability values of throughput channel, an adder, a switch group and a group of random number generators are entered into it, and the output of the clock generator is connected to the clock inputs of the generator The random group numbers and clock input of the message pulse generator, the output of which is connected to the information inputs of the group switches, the control inputs of which are connected respectively to the outputs of the group random number generators, the outputs of the group switches connected to the corresponding inputs of the adder, the output of which is connected to the input of the decryption unit .