SU1478216A1 - Device for controlling multichannel pulse trains - Google Patents

Abstract

The invention relates to digital computing and can be used to control multichannel pulse sequences in automatic operational control systems of discrete technology nodes. The aim of the invention is to increase the reliability of the control. The device contains counters of address 1 and interval 2, multiplexer 3, demultiplexer 4, mask 5 and failure registers 6, trigger 7, one-shot 8, generator 9 pulses, switch group 10.1-10.N, group of prohibition elements 11.1-11.N, group of elements OR 12.1-12.N, block 13, assignment of the analysis interval, element 14, inputs 15.1-15.N control, start start 16 and stop 17, information input 18, synchronization input 19, outputs 20.1-20.N of device failure , outputs 21.1-21.N of the register 6. The block 13 for setting the analysis interval contains the OR element, the push-button switch, the toggle register. 2 Il.

Description

ment 14, inputs 15.1-15. Controls, start 16 and stop inputs 17, information input 18, synchronization input 19, outputs 20.1-20 of the device failure, outputs 21.1-21 in the n register 6 The block 13 for setting the analysis interval contains the element OR, pushbutton switch, toggle register. 2 Il.

one

The invention relates to digital computing and can be used to control multichannel pulse sequences in automatic operational control systems of discrete technology nodes.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows a functional diagram of the device; Fig 2 is a functional block diagram of the analysis interval.

The device contains 1 address and interval 2 counter, multiplexer 3, demultiplexer 4, mask 5 and failure registers 6, trigger 7 start, one-shot 8, generator 9 pulses, switch group 10.1-Yu.p, group of elements BAN 11.1-11 „, group of elements OR 12.1-12 „p, block 13 sets the analysis interval, element I 14, inputs 15c1-15.p control, start start 16 and stop 17, information input 18, synchronization input 19, inputs 20С1-20.п of device failure , outputs 21 „1-21.p of register 6 о

The unit 13 for setting the analysis interval contains the element OR 22, the push-button switch 23 and the toggle register 24 „

The device works as follows.

In the initial state, all elements of the device memory are in the zero state. Before starting operation, the device is tuned to a subset of monitored input sequences. To do this, register 5, using inputs 18 and 19, sequentially writes the n-bit code, the unit bits of which correspond to uncontrolled input sequences. Single signals from the outputs of register 5 pass through the corresponding elements OR 12 to the control inputs of the switches 10 As a result, the switches 10 are disconnected from the like

the multiplexer inputs 3 uncontrolled sequences and connect to these inputs the generator output 9 "

In addition, on the toggle register 24 of block 13, a code is set that complements the maximum interval code (plus 5%) belonging to the monitored subset of sequences to the full capacity of the counter 2 o. Then by pressing the push-button switch 23 this code is entered into counter 2

The device begins to function after applying a pulse to the input.

0 16 start. This pulse sets the trigger 7 to the one state, which unlocks the counter 1 and opens the switch

1001 and element I 140 5

The counting input of the counter 2 begins to receive pulses from the output of the generator 9, as a result of which the interval of time begins,

0 which is 5% higher than the maximum interval for the monitored sequences.

If until the appearance of an overflow pulse at the output of the counter

From 2 to input 15.1, a pulse of a controlled sequence arrives, then it passes through a switch 1001, multiplexer 3 to the input of a one-oscillator 8, which forms a pulse along its trailing edge TU. This impulse closes multiplexer 3 for the duration of its duration, element I 14 switches the counter 1 to the next state with its leading edge, and writes the initial setup code from block 13 to the counter with the back edge of it.

After the termination of the pulse of the one-oscillator 8, the multiplexer 3 and the element 14 are opened, as a result of which the device switches to the control mode of the second pulse sequence. Subsequently, with the correct formation of all the pulse sequences, the device functions similarly to the described “After checking the nth pulse sequence, the device again goes on to control the first pulse sequence, etc.

When the device goes to an uncontrolled input sequence, the corresponding switch 10 receives the input from multiplexer 3 a pulse from the generator output 90. As a result, the device switches to the next input sequence with a minimum delay.

If, as a result of a failure or failure of the i-th controlled sequence during the time interval specified by counter 2, no impulse arrives at the device 150i, as a result of counter 2, an impulse appears at its output, through demultiplexer 4 passes to the input of the 1st bit of register 6 and sets it to a single state, fixing the failure. The output signal of the 1st bit of register 6 through the open element BANE ll.i is fed to the output 20L of the device, signaling the failure of the 1st input sequence. At the same time, this signal passes through the OR 120i element to the control inputs of the switch 00i, which connects the corresponding input of multiplexer 3 to the output of generator 9 in order to further eliminate the failed sequence from the subset monitored,

If the I50i input, on which a failure or malfunction is detected, then receives impulses, then they periodically close the ZAP-PET ll.i element, forming at its output a pulse sequence, indicating a fixed failure of this sequence, or a change in its parameters (increasing pulse period),

In the future, the device operates as described. The device stops working at

, - Q

50

5 0 5 d 5

Q

five

receipt of the signal Stop at the entrance 17.

Claims (1)

Invention Formula A device for controlling multichannel pulse sequences containing an address counter, the outputs of which are connected to the corresponding address inputs of a multiplexer, the output of which is connected to the input of a one-shot, the output of which is connected to the counting input of an address counter, characterized in that, in order to increase the reliability of the control, mask register, OR elements, switches, trigger block, set analysis interval, interval counter, demultiplexer, fault register, BAN elements, AND element, generator orp pulses, the output of which is connected to the first information inputs of the switches and the first direct input of the element I, the output of which is connected to the counting input of the interval counter, the overflow output of which is connected to the information input of the demultiplexer, the outputs of the mask register bits are connected to the first inputs of the corresponding elements OR, the outputs of which are connected to the control inputs of the switches, the outputs of which are connected to the corresponding information inputs of the multiplexer, the inverse control input of the multiplex The exora, inverse input of the element I, the input of the block for specifying the analysis interval, are combined and connected to the output of the one-vibrator, the forward output of the trigger is connected to the gate input of the first switch and the second direct input of the element I, the inverse output of the trigger, the address inputs of the demultiplexer are combined with the address inputs of the multiplexer, and the outputs are connected to the inputs of the corresponding bits of the fault register, the outputs of the bits of which are connected to the enabling inputs of the corresponding ementov inverted and second inputs of OR elements, control and information outputs specifying the analysis interval unit are connected respectively to the input of the synchronization and data inputs of counter intervals prohibiting inverted input elements combined with the second the information inputs of the respective switches and are the corresponding inputs of the control device, the information inputs and the synchronous input of the mask register, the S- and R-outputs of the trigger I ( 23 2V.A 2b Pa are respectively the information inputs, the synchronization input, the start and the stop of the device, the outputs of the BANKS elements are the outputs of the device -F1 2k to J