SU1476584A1 - Electric drive - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control DC motors. The aim of the invention is to improve the quality of regulation. The device contains a synchronization circuit 5, two reversible counters 20, 21 and a register 22 with the first and second groups of information inputs connected to the outputs of the first and second reversing counters 20, 21, respectively. The output of the register 22 is connected to the digital control unit 23. Improving the quality of regulation is provided due to the separate processing of information contained in the high and low bits of the register 22. 1 Cp f-ly, 2 ill.

Description

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This invention relates to electrical engineering and can be used in digitally controlled electric drives.

The aim of the invention is to improve the quality of regulation.

Fig, 1 shows a diagram of the drive; figure 2 - synchronization scheme.

The electric drive contains an electric motor 1, a reference frequency generator 2, a rotational speed setting device 3, a frequency divider 4, a synchronization circuit 5 with three inputs 6–8 and five outputs 9–13, RS flip-flop 14, three AND 15-17 elements, the first inputs of which are connected to the outputs of the RS flip-flop 14, the element OR 18 with the direct and inverse inputs connected respectively to the output of the first circuit AND 15 and the first output 9 of the circuit 5 synchronization, the fourth element And 19, the first input

which is connected to the output of the element 25 of the task f, is proportional to the code OR 18, reversible counters 20 and

21, a register 22 with a first and second group of information inputs and a clock output, a digital control unit 23, whose information input is connected to the output of the register

22, and the transfer enable output is connected to the second input of the fourth element And 19, the converter 24

setpoint N3, input to the control input of the setpoint frequency generator 3, and feedback frequency f. generated by the rotational speed pulse sensor 28 30. The function of synchronization circuit 5 is to temporarily assign

pulses of compared frequencies f3 and f, phase relations between which

code - voltage, current regulator 25, 35 m can be arbitrary, to the tact -

current sensor 26, adder 27, pulsed pulse sequences

rotational speed sensor 28, at- (cycles A, B, C, and D) derived from

what the input of the converter 24 is the code of the frequency of the generator 2. the voltage is connected to the information. Clocks A, B, C and D are formed with

the output of the digital regulating unit by the aid of the time of the pulse distribution 23, and the output is connected to the first inlet 29, performed on an 8-bit

The two are adders 27, the second input of which is connected to the output of current sensor 26, and the output is connected to the input of current regulator 25 connected to the motor 1.

The synchronization circuit 5 comprises a clock distributor 29 in the form of a shift register, four flip-flops 30-33, five AND 34-38 elements, the outputs of which are the corresponding outputs 9-13 of the synchronization circuit 5, the first, second and third inputs (6 7 and 8) of which are

the shift register, to the clock input 8 of which the reference frequency Ј0 is fed from the output of the generator 2. The frequency 4c of the clock pulse sequences at each of its outputs is f0 / 8, the time separation of the adjacent clock pulses in each cycle is 2Т0, where T0 is the period of the reference frequency; Triggers 30 and 32 of the synchronization circuit 5 serve as memory elements and record the fact of arrival of pulses of the compared frequencies on inputs 6 and 7. When

50

clock inputs, respectively, per-55 post111161 1 1 pulse input frequency 30 and third 32 triggers and trigger 30 (32) include a retractor distributor circuit 29. Clock nose information on the trigger 31 (33) outputs of the distributor 29 are connected and elements And, 34, 35 (36, 37, 38), respectively, to the inputs of the elements And allowing control to the input D of the trigger 34, 36, to the input of the element And 35 and the clock input of the trigger 33, to the input of the element And 37, to the input of the element And 38

and the clock input of the trigger 31. The output of the trigger 31 is connected to the inputs of the elements 34, 35, and the output of the trigger 33 is connected to the inputs of the elements 36-38. The drive operates as follows

in a way.

The electric drive is a dual-circuit system of the subordinate control of the rotation frequency of the DC motor 1. Inner contour

Current control of the motor core is made analog based on current regulator 25, which includes a thyristor or transistor power converter, with negative current feedback from the motor core from current sensor 26. The external circuit for adjusting the rotational speed is digital. The inputs 6 and 7 of the synchronization circuit 5 receive the frequency

set f, proportional to code

setpoint N3, input to the control input of the setpoint frequency generator 3, and feedback frequency f. generated by the rotational speed pulse sensor 28. The function of synchronization circuit 5 is to temporarily assign

pulses of compared frequencies f3 and f, phase relations between which

the shift register, to the clock input 8 of which the reference frequency Ј0 is fed from the output of the generator 2. The frequency of the clock pulse sequences at each of its outputs is f0 / 8, the time separation of the adjacent clock pulses in each cycle is 2Т0, where T0 is the period reference frequency, Triggers 30 and 32 of synchronization circuit 5 serve as memory elements and record the fact of arrival of pulses of compared frequencies on inputs 6 and 7. When

Hera 32 (33). The synchronization circuit 5 operates according to the three-stroke circuit, so that, for example, the clock pulse D (B) polls the trigger state 31 g (33), and the clock pulses A and B (C and D) form the pulses at outputs 9 and 10 (12 and 13) synchronization circuits 5, thus ensuring their rigid temporary separation. The output pulse name at the R input returns to the initial state the triggers 30 (32), after which the next beat of the D stroke (B) returns to the initial state the trigger 31 (33) at the C input, 15 since this time at the input D of the last — already the level of logic O occurs. To exclude the occurrence of significant disturbances from the deviation of the phase shifts of the pulses f and foc caused by the forced temporal reference, the level of the clock frequencies is chosen significantly higher than the maximum possible level of the frequencies f, and foc. 25

In the stationary mode, with equal frequencies of the reference and feedback, the pulses of these frequencies, synchronized respectively by cycles B and D with output 10 and 13 of the synchronization circuit, are alternately fed to the set inputs of the RS flip-flop 14 and switch it with the frequency F5 foc In this case, the duty cycle of following rectangular pulses at the outputs of the trigger-, 5-gera 14 is constant and is determined by the established phase shift between the pulses of both input sequences.

40

At the second input of the element And 16,

controlled by the signal from the direct output of the trigger 14, the output frequency of the setpoint 3 comes in, is equal to kfj ,, rfle k - the division factor of the 4 .c frequency divider. In this mode, at the output of the element 16, in each switching cycle of the trigger 14 a pair of pulses of frequency kfj is generated at the counting input of counter 21. Resetting counter 21 at input R of pro-50 is depleted by each feedback frequency pulse synchronized with clock A Thus, in each cycle, in the time interval between D and A cycles, a code is stored in the counter, the value of which is proportional to the time the trigger 14 was in state 1, i.e. phase shift

between pulses f, and fpc in stationary mode. It is obvious that the value of the code N "may lie in the range from 0 to k, for a certain phase shift of the pulses of the frequencies f e and foc permanently and does not depend on their absolute value, and hence on the value of the frequency of rotation. Taking into account transients and dynamic modes, the rotational frequency controller will not ensure normal operation with a null body that fixes phase mismatches only within one period of compared frequencies. An integrator is needed that can fix the integral phase mismatch of frequencies greater than one period (or 2fr). In the electric drive, the digital integrator consists of two counters 20 (works in the reverse mode) and 21 (works only in the direct account mode). The transfer output P + of counter 21 is connected to the addition input of counter 20, the subtractive input of the latter is connected to the output of element AND 17, which is controlled from the inverse input of trigger 14. The information input of element And 17 comes from output 11 of synchronization circuit 5 frequency pulses feedback synchronized with the clock cycle C. The capacitance of the counter 21 is chosen equal to K. In view of this, when the phase mismatch exceeds one period of the reference frequency, the counter 21 overflows and the number of integer error periods is recorded in the transfer circuit 20

N,

The latter takes place in transient conditions.

When the engine is accelerated from zero to the moments when the feedback circuit pulses are not yet present, the information transfer pulses in register 22 are synchronized with clock A from output 9 of synchronization circuit 5 and arrive through element 15 at the input of element 18 when the trigger 14 is in nii 1.

When the set reference code changes in the direction of slowing down the rotation speed, the counting input of the subtraction counter 20 begins to flow through the element 17, the trigger 14, the feedback pulses synchronized with the step C. The latter occurs when two or more feedback frequency pulses arrive. in the absence of setpoint frequency pulses.

Since the cycle C is ahead of the cycle T, then in the stationary mode the specified pulse does not pass through the element 17, since in each cycle by the time of the cycle C the latter turns out to be a blocked zero signal from the inverse output of the trigger 14.

Taking into account that the capacity of counter 21 is chosen equal to K 2, where m is the number of binary bits of counter 21, and K, as shown above, is a measure of phase mismatch in one period, K corresponds to the value of the low-order number written in counter 20. Therefore, in all cases, the value of the integral mismatch of the frequencies N NI + N is formed in the counters

The processor, element 19, is blocked from the output of the digital regulator (a device with a short signal to remove the resolution for the transfer of information to block 23.

In accordance with the programmed law of regulation (PI, PID) at the output of block 23 on each cycle

The resolution discretization code 10 generates a control action code, which, after being converted into an analog converter 24, is fed to the input of current regulator 25. The presence of a programmable digital control unit in combination with an integral zero-body that provides tracking with discreteness, K times smaller than the quantization step of the pulse sensor Chas21 and 20 as the value of a single (m + n) - 20 TOTS of rotation, allows you to create a bit binary code, where n - the number of bits of the counter.20, the latter forms the highest bits of the code N.

a highly accurate system with a large depth of regulation that implements various laws of regulation depending on the characteristics of the objects and the N code value in each cycle of peg 25 process requirements,

which involves a drive mechanism.

Claims (2)

1. An electric drive containing a motor, serially connected reference frequency generator, frequency adjuster, frequency divider, as well as synchronization circuits, RS-trigenerates into register 22 when received at the clock input of register 22 through the reference pulse OR 18 and 19 elements synchronized tact D from the output 12 of the circuit 5 synchronization. Thanks to the use of inverse. the input element OR 18 transferring information to the register 22 is performed at the falling edge of the clock cycle D, while blocking the counting of the pulses of the frequency kf from the output of the element I 16, I produce at the leading edge of the clock D, when the trigger 14 on the E input returns to the original condition. Thus, on each cycle of the frequency of the assignment to the register 22, the transfer status is set, the value of which strictly corresponds to the integral mismatch of the frequencies of the assignment and feedback. The control algorithm in the speed control loop is programmed in a digital control device, which is a micro-computer with a standard structure including a microprocessor, a memory device, a timer, and input / output information elements. At intervals determined by the microprocessor, the contents of register 22 are transferred to the digital control unit 23 in order to prevent the transfer of information to the register at the time of the request of the micro30 40 35 „ a hero, two elements And, two reversible counters and a register with the first and second groups of information inputs connected to the outputs of the first and second reversible counters, respectively, the converter code - voltage, current regulator, to the output of which the electric motor and the rotary pulse frequency sensor are connected, The 45 inputs of the synchronization circuit are connected to the outputs of the frequency divider, the pulse frequency rotation sensor and the reference frequency generator, respectively; the direct and inverse outputs of the RS flip-flop are connected to the first inputs with correspondingly, the first and second elements I, the second input of the first element I is connected to the output of the rotational speed setting unit, and the output is connected to the summing input of the second reversible counter, i.e. increase the accuracy of regulation, it introduced the third and fourth elements 50 55 The processor, element 19 is blocked from the output of the digital regulator (a device with a short signal to remove the permission for transferring information to block 23. In accordance with the programmed law of regulation (PI, PID) at the output of block 23 on each cycle the discretization of the solution produces a code of regulating action, which, after being converted into analogue by converter 24, is fed to the input of current regulator 25. The presence of a programmable digital control unit in combination with an integral zero-body, which provides tracking with discreteness, is K times smaller than the quantization step of the pulse sensor H1. Electric drive containing a motor, serially connected reference frequency generator, frequency adjuster, frequency divider, as well as synchronization circuits, RS-trig0 five" a hero, two elements And, two reversible counters and a register with the first and second groups of information inputs connected to the outputs of the first and second reversible counters, respectively, the converter code - voltage, current regulator, to the output of which the electric motor and the rotary pulse frequency sensor are connected, 5, the inputs of the synchronization circuit are connected to the outputs of the frequency divider, the pulse rotational frequency sensor, and the reference frequency generator, respectively; the direct and inverse outputs of the RS flip-flop are connected to the first coaxial inputs correspondingly, the first and second elements I, the second input of the first element I is connected to the output of the rotational speed setting unit, and the output is connected to the summing input of the second reversible counter, i.e. increase the accuracy of regulation, it introduced the third and fourth elements 0 five 7 And, OR element with direct and inverse inputs, digital control unit connected between the register output and the converter input code - voltage, adder connected between the converter code output - voltage and current regulator input, current sensor whose output is connected to the second input of the adder, and the synchronization circuit is equipped with five outputs connected respectively to the first input of the third element I, to the S input of the RS flip-flop, to the input of setting the second reversible counter, to the second input of the second element And to the R input The RS flip-flop, inverse and direct inputs of the OR element are connected respectively to the R-input of the RS flip-flop and the output of the third element AND, the second input of which is connected to the direct output of the RS flip-flop, the first and second inputs of the fourth element And are connected respectively to the output of the element OR and the transfer resolution output of the digital control unit, and the output is connected to the clock input of the register, the addition and subtraction inputs of the first reversible counter are connected respectively to the transfer output of the second reversible counter and the second output item I. 2. Electric drive according to p-, i, characterized in that the sync circuit eight 0 five The clock contains a clock distributor in the form of a shift register, the clocking input of which is the third input of the synchronization circuit, four flip-flops with clocked, set and control inputs and five AND elements, the outputs of which are the corresponding outputs of the synchronization circuit, and the clocking inputs The first and third triggers are respectively the first and second inputs of the synchronization circuit, the control inputs of the second and fourth triggers are connected to the forward outputs of the first and third triggers, ne stems inputs of first and second AND gates are connected to a direct output of the second flip-flop, the first inputs of the third, fourth and fifth AND gates are connected to a direct output of the fourth flip-flop, the zero setting inputs of the first and third flip-flops connected to outputs of the second and fifth element ' 5 cops And, the first output of the clock distributor is connected to the second inputs of the first and third elements And, the second output is connected to the second input of the second element AND and clocked on the fourth trigger input, the third output is connected to the second input of the fourth element And, the fourth output is connected to the second input p the element And the clock input of the second trigger. 0 five