SU1474567A1 - Method and apparatus for checking measuring comparators - Google Patents

Abstract

This invention relates to the control of measuring devices, in particular comparators. The purpose of the invention is to improve accuracy. The method is implemented in a device in which the signals of the source 1 of the constant test signal and the generator 2 of the randomly varying signal are supplied to the calibrated and exemplary comparators 3 and 4, respectively. The state of the comparators' outputs is monitored by the triggers 5 and 6, the information from which is transmitted to the elements 7.8 matches and decision block 9. The receipt of information through the elements 11 and 14 of the delay at the inputs of the digital comparator 13 and the element IS-HE 13 is carried out on a clock pulse of the generator 10 pulses of a stable frequency. The iterative process of estimating the accuracy of a calibrated comparator 3 is organized on a reversible counter 15 using an inverter 16 and a setting device 17. 2 sec. f-ly, 3 ill.

Description

Јъ

one

4b

SL O

This invention relates to electro. measuring equipment and is intended for calibration (certification) of automatic control systems.

The purpose of the invention is to improve the accuracy of calibration of measuring comparators by controlling their static and dynamic metrological (accuracy) characteristics, taking into account the random error of control.

The method is carried out as follows.

The mathematical expectation of the delay between the edges of the same name, - (positive or negative) output signals of the calibrated and sample measuring comparators, is measured; the initial interval of the front of the output signal of the reference measuring signal is entered.

the comparator, when comparing the moments of occurrence of the same edges of the output signals of the measuring comparators, change (adjust) the initially entered delay interval

by a time quantum multiple of the maximum allowed delay interval, but shorter, up or down, respectively, with advanced or late moments of occurrence of the same edges of the output signals of a delayed one relative to another of the specified measuring comparators, the last action is repeated

raters associated with the amplitude-frequency-20 number of times, with the magnitude of non-identical linear characteristics of the exemplary and verifiable

(certified) measuring comparators are determined by their amplitude-frequency characteristics and dispersions and their own random noise dispersions of measuring com- pounds by expressions.

To measure the mathematical expectation of the intrinsic additive noise of a given delay, simultaneously — through the measured value of the mattress — is applied to the corresponding input expectations between the same name of the test (attestable) and the image (positive (rf) or negative measuring comparatory (l ) by the fronts of the output sig- nally varying signal from the equal frequencies of the reference and verified (by the atomic spectrum within the range of the tested) measuring comparative transmissions of the reference measuring instruments from expressions

sixteen

 + N. f IlMjuQI - tKcCioOlM dw |

WB

 ) il d

S

one

Ui-ui N 1) 1- - iKaCjw) 1} dw

about .

N, B | Kn (jW)) aw1du

de M {tn "ii,.

 - the mathematical expectation is 45 times the duration of the delay intervals, respectively, between positive and negative edges of the output signals;

U0 (juO |,

| Kp (jui) - modules of amplitude

frequency characteristics of the reference and calibrated measuring comparators)

frequency characteristics and variance (1)

S

(2)

 P

, are the variances of the own additive noise of the model and calibrated measuring comparators;

Nc is the intensity of the uniform spectrum of a randomly varying test signal;

S is the upper limit of the frequency band, in which non-identity is measured. raztsovogo and verified measuring comparators, installed

14

in the limit equal to the upper boundary frequency of the reference measuring comparator.

To derive equality connecting the mathematical expectations of the squares of the duration of the delay intervals, for example, between the positive fronts of the output signals of the sample and verified measurement comparators with the dispersions of the own additive noise of the sample and verified measurement comparators, the amplitude-frequency characteristics of the sample and verified measurement comparators and parameters of the test signal will present the algorithm of the proposed device in the form of an adequate iteration onnogo expression

, enf (n + t) t "(ndt)., (to + ndt) - U3 -,

- htye (te + ndt, (ndt)) + + 40 (to + nut + „, () - UJ},

where С „f (p +

+1) 4 tj, iXndt) -duration of the delay intervals on (n + 1) -m and n-th measurement cycles i

& t is the pulse following period

lira Ms htyi (t, + nAt) + n.1 (t + n / Jt) lim M ,, 4Jhtyb (t6 + nJt +

+ „4, (+ ()) - Uj}

it lim D, (tc + ndt) + 4, (t0 + nut) - U - hryc (t0 + nflt + „+

+ TP ()) + 1e (t0 + n & t +)) - C, de MVi + llit-K

M. -} - operators of mathematical expectation 50 for the specified random variables;

u, h, with

Yiw. (-), 55

let) random sequences, independent of each other, which follows from phi5674

stable frequency generator; y, () and 5y0 (to + n4t +

+ n (n / 3t)) are the output signals of the measuring comparators of the turnable and obraztsovogo, respectively, at the specified times l., (te + ndt) and 15le (te + n-St +

f + nop (ndt)) - additive noise

calibrated and exemplary measuring instruments, respectively, at the indicated times

of time

| i, e, o

| 0, 9 - 0,

where 6 is the value of the function argument

U indicated in the formula is the value of a constant test signal that is applied to the second inputs of the test complex. For the convergence of the algorithm presented in the iterative form (3), it is necessary and sufficient that the conditions

(four)

(five)

the essence of the device operation} -} is the dispersion operator for the same random sequences)

C is a certain constant value that determines the random component of the attestation error.

514 74

Permanent C is selected based on the technical and economic requirements that are imposed on the appraisal device. 5

The output signals y (), Vc () and noise C, (1) 10 () are distributed normally, since a positive random process with a normal 10 distribution law is applied to the inputs of the measuring comparators. Therefore, equality (5) after conversion by the expectation operator is reduced to

 . (and), (6)

where Fu, + i., (U), v о to (U) Laplace functions, which can be represented in a normalized form

U

6g +

V1

 f (.

U

.

) (7)

or

U

U

VAtt

(eight)

where does equality come from

, one

 Vo

b +6 6 +61

(9)

V t g "

In order to find out from the obtained equality, explicitly, the desired value of the expectation of the durations of the delay interval is the output signal of an exemplary measuring comparator with a second-order error of smallness in the following form:

yb (t0 + ndt + / aB4 (nut)) y (to + (10 + ndt) + y0 (t0 + n, at) -Dn4, (nAt),

where V0 () is the first derivative of the output signal of the reference measuring comparator at the specified time.

Determine the variance for all specified random variables, get with the error of the second order of smallness

6l (t0 + nflt + fnit (ndt))

CV

6V

HS P4 (nat) r (o), (11)

five

0

Where

PP

(about) ()

the dispersion of the output signal of the reference measuring comparator without taking into account the additive noise, the second derivative of the autocorrelation function of the same output signal at the zero point (i.e. with Ј пф (ndt) 0)}

))

- second starting point equal to

 (n / tt)) + + M (, (n / lt)))

When deriving a formula, it is taken into account that for a normal random process its value and the value of the first derivative are independent at coinciding times. You can choose a reverse counting ka such that

(n4t)) ЈM (€ n $ (n4t) j2. Therefore (n4t) l))} 1.

The equivalent circuit of the measuring comparator consists of a series-connected non-sparking nonlinear link and an inertial linear link. Therefore, the dispersion of the output signal and its autocorrelation function can be expressed in terms of the moduli of the amplitude-frequency characteristics of the model and calibrated measuring comparators. Substituting the corresponding values of the amplitude-frequency characteristics moduli into equality (9), taking into account the fact that the input signal has a uniform spectral density in the frequency band (O, WB), we obtain the following

above expression.

Figure 1 shows the functional diagram of the device j in figure 2 - a digital comparator; FIG. 3 shows a decision block.

A device for calibrating measuring comparators contains a source of 1 constant test signal, a generator 2 of a randomly varying test signal, the outputs of which are connected to the first and second SECOND inputs of the measured turntable 3 and sample 4 comparators, whose outputs are connected to the first (gate) inputs of the trigger 5 and 6, respectively, the direct outputs of which are connected: the first trigger 5 - with the first input of the first element 7 of the match, the second trigger 6 - with the first inputs of the element 8 are the same and the decision block 9, the second inputs of the matching elements 7 and 8 are connected to the output of the generator 10 stable frequency pulses, the output of the first matching element 7 is connected to the first inputs of the digital comparator 12 and an increased time through the delay element 11 propagation delays, the output of the second coincidence element 8 is connected to the first input of a controllable delayed unit 14, the second input of which is connected to the same inputs of the decision block 9, the OR-NOT 13 logic element, reversing Meters withstand 15 input logic inverter 16 - with high latency, and external

the Start device's input, the output of the controllable delayed unit 14 is connected to the second input of the digital comparator 12 and the third input of the OR-NOT 13 logic element, the output of which is connected to the second inputs Reset of the flip-flops 5 and 6, and the third D-inputs of which are connected to the Stop output 9 make decisions, the first Smaller and the second. More outputs of the digital comparator 12 are connected respectively to the first subtractive and third summing inputs of the reversible counter 15, the first count output of which is connected to the third inputs of the controlled delay block 14 and the decision block 9, the second Less zero and the third Overflow outputs of the reversible counter 15 are connected respectively to the fourth and fifth inputs of the decision block 9, the output of the logic inverter 16 is connected to the fourth input of the reversible counter 15, the fifth input of which is connected to the output master 17 of the code.

Digital comparator 12 () contains three logical elements NAND 18-20, the first inputs of the elements

AND-NOT 18 and 19 are connected to the first external input of a digital comparator, the second inputs of the elements AND-NOT 18 and 20 5 are connected to the second external input of the digital comparator, the output of the element AND-NOT 18 is connected to the second and first inputs, respectively, of the elements E 19 and 20, the outputs of which VU are respectively the second and third outputs of the digital comparator. The decision block 9 (FIG. 3) contains a code comparison element 21, a counter 22, logical elements OR

23 and 24, the first inputs of which are the external inputs of the block, the third, first, fourth and fifth, respectively, and the second input of the block — the second input of the counter 22, setpoint 25 and 26 of the codes, defining the tolerance value and the number of iterations respectively (comparisons ), the outputs of which are connected to the second inputs, respectively, of elements 21 and 27

5 code comparisons, the outputs of the code comparison elements 21 are connected respectively: the first Less is to the first input of the coincidence element 28, the second More and the third Equal to

0 the first and second inputs of the logic element OR 29, the output of which is connected to the first input of the matching element 30, the output of the counter 22 is connected to the first input of the element 27

from comparison of codes, the output of which is connected to the second inputs of elements 28 - and 30 matches, the outputs of which are connected to the second inputs, respectively, of the logical elements OR 23

Q and 24, the outputs of the latter are connected respectively to the first and second inputs ... of the indication element 31 and the logic element OR 32, the output of which is the external output of the Stop unit.

The device works as follows.

The constant and randomly varying test signals from the outputs, respectively, of the source t of the constant test signal and the generator 2 of the randomly varying test signal are compared to a testable 3 and an exemplary 4 measuring comparators and pulse signals appear on their outputs, due to the nonidentity of metrological ( accuracy characteristics of comparators are shifted

five

0

five

relatively same each other (positive and negative) fronts. The device starts with an external positive impulse. Start, which is used to reset the reversible counter 15 and counter 22 of block 9 (FIG. 3) and the initial installation of the internal counter of the controllable delayed block 14, while 1 is set to D-inputs of triggers 5 and 6, with some delay, a negative pulse (inverted start pulse) is generated at the output of logical inverter 16, as well as at the output of the YLI-NE 13 logic element, and the code 15 is set at the output of the counter, specified by a code setting unit 17, and resets flip-flops 5 and 6, after which the device is carried out cyclically work. Each cycle starts with setting 1 of any of the triggers 5 and 6 along the first positive (or negative) front of the output signals of the measuring comparators 3 or 4 and ends with resetting the triggers 5 and 6 by a pulse from the output of the OR-NOT 13 element. following; the high output level of each trigger 5 and 6 opens, respectively, an element 7 or 8 coincidence for the passage of pulses from the generator 10, while the pulses from the output of the coincidence element 8 are delayed by the controlled delay unit 14 by the number of periods specified by the inverse code on its third output, which in l each cycle is rewritten into int. The first counter of the unit 14 is the first pulse arriving at its first input.

At the output of the controlled delay unit 14 and, therefore, at the second input of the digital comparator 12, the front is shifted relative to the leading edge of the first pulse transmitted through the coincidence element 8 by a predetermined discrete time delay. If the first input of the digital comparator 12 from the beginning of the cycle until this moment did not come from the output of element 7 coincidence, this means that the input discrete delay of the output of the output signal of the model comparator 4 is less than the actual current delay of 147456710

To whom the front of the output signal of the measuring instrument being compared is 3. If both edges of the digital comparator 12 have fronts at the same time, this means that the entered and actual current delays are equal, but if the front of the first input of the digital comparator 12

20

25

TQ earlier than its second input, Oeto means that the front came first to the trigger from the output of the calibrated measuring comparator 3. These conditions are fulfilled with an error of 5 discreteness determined by the period of the clock pulse 10 of the generator.

The delay element 11 compensates for the spurious delay of the signal in block 14 of the controlled delay. In accordance with the above conditions, the digital comparator 12 (FIG. 2) in the first and third cases produces a negative pulse, respectively, at the first output Less and the second output More, 1 in the second case leaves the high levels of both outputs unchanged, and the reversible counter 15 reduces

Zero or increases by 1 the output code on the back (positive) edge of the pulse, applied respectively to the first or third of its inputs. The OR-NOT 13 element on any positive pulse at its inputs produces a negative pulse, resetting triggers 5 and 6 to the initial zero state and delayed relative to the input by such a delay, which guarantees the operation during this time of the digital comparator 12 and the reversible counter 15.

The decision block 9 operates as follows (Fig. 3). Counter 22 counts the number of actuations of the device trigger 6 and, when this number reaches the value specified in the unit 26, the code (the number of iterations), the code comparison element 27 opens elements 2b and 30 matches. The code comparison element 21 compares the current inverse code of the input delay interval with the specified tolerance value and, when the device performs a specified number of iterations, the result of the comparison with its outputs goes through the open elements 28 and 30 matches and the elements OR 23 and 24 to the inputs of the block 31 in35

40

45

50

55

0

five

earlier than at its second input, Oeto means that the front came first to the trigger from the output of the calibrated measuring comparator 3. These conditions are met with discretization errors determined by the period of the generator 10 clock pulses.

The delay element 11 compensates for the spurious delay of the signal in block 14 of the controlled delay. In accordance with the above conditions, the digital comparator 12 (FIG. 2) in the first and third cases produces a negative pulse, respectively, at the first output Less and the second output More, 1 in the second case leaves the high levels of both outputs unchanged, and the reversible counter 15 reduces

o or increases by 1 the output code on the back (positive) edge of the pulse, applied respectively to the first or third of its inputs. The OR-NOT 13 element on any positive pulse at its inputs produces a negative pulse, resetting triggers 5 and 6 to the initial zero state and delayed relative to the input by such a delay, which guarantees the operation during this time of the digital comparator 12 and the reversible counter 15.

The decision block 9 operates as follows (Fig. 3). Counter 22 counts the number of actuations of the device trigger 6 and, when this number reaches the value specified in the unit 26, the code (the number of iterations), the code comparison element 27 opens elements 2b and 30 matches. The code comparison element 21 compares the current inverse code of the length of the input delay interval with the specified tolerance value and when the device performs a specified number of iterations, the result of the comparison with its outputs goes through the open elements 28 and 30 matches and the elements OR 23 and 24 to the inputs of the block 31 in5

0

five

0

five

eleven

diction If during the operation of the device its reversible counter 15 generates one of the signals Overflow or Less than zero, these signals arrive through the elements OR 23 or 24 to the inputs of the display unit 31.

If there is 1 on the first or second inputs of the display unit 31, the result of the Scoring or Gaud calibration is displayed in it, respectively, and the output level of the OR 32 element is set to the logic level O, which is the Stop device signal.

Formula of invention

1. The method of verification of measuring comparators, which consists in supplying test signals to both the calibrated and exemplary measuring comparators simultaneously, determines and compares the monitored parameters with a predetermined value, judging by the comparison result that the measured measuring comparator is valid. in order to increase the reliability of verification, a randomly varying signal with a given intensity and with a uniform signal is used as a test signal as a test signal based on the measurement spectrum comparator, the front of the output signal of the reference measurement comparator is formed by a certain delay interval, the moments of appearance of the fronts of the output signals of the measurement comparators are compared taking into account the delay, the delay interval is changed by a time quantum in the direction of decreasing or increasing respectively or a lag in the appearance of the front of the output signal of the measuring instrument being compared with respect to the output signal of the measuring signal The comparator is used to change the delay interval for a given number of edges of the output signals of the measurement comparators. The duration of the delay interval is used as a monitored parameter.

2. A device for calibration of measuring comparators containing a constant test source

20

25

47456712

signal, an exemplary measuring comparator, terminals for connecting the inputs and output of a calibrated measuring emulator, a delay comparator, a digital comparator, a decision-making unit, a constant test signal source output connected to a terminal for connecting a first input and a first input model measuring comparators, the output of the delay unit is connected to the first input of a digital comparator, characterized in that,

15 in order to increase the reliability of verification, a generator of a randomly varying test signal, the first and second triggers, the first and second elements of a match, a stable frequency pulse generator, a logical NAND unit, a controllable delay unit, a reversible counter, a logic inverter, code sensor, while the generator output is randomly varying the test signal is connected to the terminal for connecting the second input of the turnable and the second input of the sample measuring comparators, the output of the sample the measuring comparator is connected to the first inputs of the first trigger, the terminal for connecting the output of the rotating comparator is connected to the input of the second trigger, the output of the first trigger is connected to the first input of the first matching element, the output of the second trigger and the decision unit, the second the inputs of the coincidence elements are connected to the output of a stable frequency pulse generator; the output of the first coincidence element is connected to the input of the delay unit, the output of which is connected to The first input of the logical element OR NOT, the output of the second coincidence element is connected to the first input of the controllable delay unit, the second input of which is connected to the same inputs of the decision block, the logical element OR NOT, the reversible counter, the input of the logical inverter and the external trigger input, the output of the controllable delay unit is connected to the second input of the digital comparator and the third input of the OR-NOT logic element, the output of which is connected to. the second inputs of the first and

thirty

35

40

45

50

55

the second triggers, the third inputs of which are connected to the output of the decision block, the first and second outputs of the digital comparator are connected respectively to the first and third inputs of the reversible counter, the first output of which is connected to the third inputs of the controlled delay block

and the decision block, the second and third outputs of the reversible counter are connected respectively to the fourth and fifth inputs of the decision block, the output of the logic inverter is connected to the fourth input of the reversible counter, the fifth input of which is connected to the output of the setpoint generator.

FIG. 2

Claims (2)

Claim 1. The method of verification of measuring comparators, which consists in sending test signals to the calibrated and reference measuring comparators at the same time, monitored parameters are determined and compared with the set value, the result of the comparison is used to judge the validity of the calibrated measuring comparator, characterized in that, in order to increase reliability of verification, a randomly changing signal with a given intensity and with a uniform sample bandwidth is used as a test signal the first measuring comparator by the spectrum, form the delay of the front of the output signal of the standard measuring comparator for a certain delay interval, compare, taking into account the delay, the moments of the appearance of the fronts of the output signals of the measuring comparators, change the delay interval by a time quantum in the direction of decreasing, decreasing or increasing, respectively, when leading or the delayed moment of the appearance of the front of the output signal of the calibrated measuring comparator relative to the output signal of the measuring sample new comparator, carry out a change in the delay interval for a given number of fronts of the output signals of the measuring comparators, the obtained duration of the delay interval is used as a controlled parameter. 2. A device for checking measuring comparators, containing a source of a constant test comparator, terminals for connecting the inputs and outputs of the calibrated measuring comparator, a delay unit, a digital comparator, a decision block, the output of a source of constant test signal is connected to the terminal for connecting the first input of the calibrated and the first input exemplary measuring comparators, the output of the delay unit is connected to the first input of a digital comparator, characterized in that, 15 in order to increase the availability The calibration pattern includes a randomly varying test signal generator, first and second triggers, first and second coincidence elements, 20 stable frequency pulse generator, NAND logic element, controlled delay unit, reversible counter, logical inverter, code generator, the output of the generator 25 of a randomly varying test signal is connected to the terminal for connecting the second input of the calibrated and the second input of the reference measuring comparators, output 30 of the reference measuring computer the rotor is connected to the first inputs of the first trigger, the terminal for connecting the output of the verified comparator is connected to the input of the second trigger, the output of the first trigger is connected to the first input of the first match element, the output of the second trigger is connected to the first inputs of the second match element and decision block 40, the second inputs of elements coincidences are connected to the output of the stable frequency pulse generator, the output of the first coincidence element is connected to the input of the delay unit, 42 whose output is connected to the first input of the OR-HE logic element, the output of the second coincidence element is connected to the first input of the controlled delay unit, the second input of which is connected to the same inputs of the decision block, OR-HE logic element, a reversible counter, the input of the logical inverter and an external trigger input, the output gg of the controlled delay unit is connected to the second input of the digital comparator and the third input of the OR-HE logic element, the output of which is connected ς by the second inputs of the first and fourteen J3 1474567 of the second triggers, the third inputs of which are connected to the output of the decision block, the first and second outputs of the digital comparator are connected respectively to the first and third inputs of the reversing counter, the first · output of which is connected to the third inputs of the controlled delay unit and the decision block, the second and third outputs of the reverse counter are connected respectively to the fourth and fifth inputs of the decision block, the output of the logical inverter is connected to the fourth input of the reverse counter, the fifth input of which · union of soybeans with the release set point code.