SU1467787A2 - Device for receiving multiposition apparatus - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the quality of reception by ensuring its control. The device contains a threshold unit 1, shift register 2, equivalence el-3, switch 4, adder 5, inverter 6, memory block 7, comparator 8, buffer register 9, inverter 10, counter 11, r-r 12 clock pulses, a divider 13, an information register 14 and an evaluation unit 15, consisting of an inverter 16, an adder 17, an error register 18, a decoder 19, an EL element OR 20, 25, 28 and 31, an And 21, 22 and 30 el, a counter - splitter 23, splitter 24, a totalizer of its counter 26, comparison blocks 27 and 29, and evaluation register 32. The goal is achieved by introducing an estimator 15, which converts the coincidence codes into mismatch codes, processes them appropriately and generates signals of a probabilistic assessment of the quality of receiving discrete information. I il. S

Description

The invention relates to telecommunications, can be used in transmission systems of discrete data and is an improvement of the invention by ed. St.

No. 853819.

The purpose of the invention is to improve the quality of reception by ensuring its control.

The drawing shows a structural electrical diagram of the proposed device.

The device contains a threshold block 1, shift register 2, equivalence elements 3, switch 4, adder 5, inverter 6, memory block 7, comparator 8, buffer register 9, inverter 10, counter 11, clock generator 12, divider 13, register 14 information, the evaluation unit 15, consisting of an inverter 16, an adder 17, an error register 18, a decoder 19, a first OR element 20, a third And element 21, a first And element 22, a divider counter 23, a divider 24, a second OR element 25, a totalizing counter 26 , the first block 27 comparison, the third element OR 28, the second block and comparison 29, the second AND gate 30, a fourth OR gate 31 and the register 32 assessment.

The device operates as follows.

The input signal, which carries information, is a multi-position biorthogonal code of length N, which, when received, is decoded with error correction.

For the period of following the symbols of the input biorthogonal code using the threshold block 1, shift register 2, equivalence elements 3, switch 4 and adder 5, the received signal is compared with each of the reference codes, the number of matches between which in the parallel binary code is generated at the output of adder 5. The selection of one of the reference codes corresponding to the maximum of the cross-correlation function with the received signal is carried out by an inverter 6, a memory unit 7 and a comparator 8, the output signal of which is recorded binary code of the number of matches in the memory unit 7, as well as the corresponding information code coming from the counter 11 through the inverter 10 to the buffer register 9.

After the end of N cycles, a code corresponding to the maximum of the mutual correlation function of the received signal and one of the reference codes is recorded in the buffer register 9. This combination is read into the information register 14 by a signal from divider 13. During the next cycle of the device, which lasts t = N · to, where t ₀ is the clock frequency of shift register 2, information from the output of register .14 is sent to the subscriber.

Simultaneously with the information code being written to register 14 by the signal of divider 13, the corresponding binary parallel code of the number of matches from block 7 of the memory is supplied to the inputs of block 15. Block 15 converts the match codes coming from the outputs of block 7 into mismatch codes, processes them accordingly and generates signals of probabilistic assessment of the quality of reception of discrete information. Coincidence codes A are received at the inputs of the inverter 16,, θ, which are the inputs of block 15. The adder 17 is an M-bit adder, the first term, the inverted match code A, is sent to the inputs of the inverter 16 and the pre-set match code A is set on the other 15 additional inputs M low-order bits of the code of the number Ν + 1, where N is the bit depth of the received code; M is the minimum number of digits required to represent the number Ν.

Thus, at the output of the adder 17, an M-bit mismatch code R

R = N — A, which according to the signal from the output of the divider 13 25 is recorded in register 18.

The reception quality of multi-position complex signals is characterized by the magnitude of the error rate in the received information, where, by is the number of erroneously received information symbols;

B - information transfer rate; T is the duration of the evaluation cycle.

Therefore, in order for the evaluation node to select 35 specified gradations of quality N <? M, Not, moreover, No * ui <Νοίιι, in accordance with (1), it is necessary to fix the corresponding n </, not erroneous decoding. Given that the probability of erroneous decoding is n Nf S- R

R '· (N — R) · 2 ^s (2) where R = j, .. „[N / 4]; ] =! ..., [N / 4-1];

S is the number of allowed combinations, then, having set a certain value j, based on the possibility of obtaining an estimate for an acceptable assessment cycle for the duration, it is possible to estimate the number of mismatches Z * for which erroneous decoding will occur with a predetermined probability Q.

d - Q> 1 garden ^{1δ (} ΪΝ74Ϊ ~ Ι + ϊ 'f, Qr)

In addition, erroneous decoding occurs at R = N with Q = l.

The decoder 19 selects the mismatch codes for the selected interval of the values R = j, ..., [N / 4] and R = N. The conclusions of the decoder 19, corresponding to the mismatch codes R = j, ..., [N / 4], are connected to the inputs of the OR element 20, the output of the decoder corresponding to 'R = N is connected to the input of the element And 21. According to the signal from the divider 13 s the output element And 22 signals are fed to the input of the counter-divider 23, the coefficient of which K = Z *. At the other input of the counter-divider 23, signals from the end of the evaluation cycle from the output of the divider 24 are received, setting the counter-divider 23 to zero.

The signals of the end of the evaluation cycle are generated by the divider 24 by dividing the input signals generated by the divider 13 by a predetermined division coefficient corresponding to the duration of the evaluation cycle. Summing counter 26 counts the number of signals © generated by the counter-divider and element And 21 for the estimation cycle, and Θ is the number of erroneous decodings per evaluation cycle. At the end of the evaluation cycle, the totalizing counter is set to zero by the signal from the output of the additional divider.

Since on one erroneous decoding, on average, β errors occur in the received information, where β is the average distance between information code combinations, then π, = β. · Θ. (3)

Taking into account (1) and (3), the number of erroneous decodings corresponding to the given gradations of quality Ν ™ and GC * w, @ - ^N ° '' ^T β = ^Ν ° ^ω · β · ^T Μ)

Codes of quantities © ι and © ₂ , previously calculated in accordance with (4), are installed on additional inputs of the first 27 and second 29 comparison blocks. The code числа from the outputs of the totalizing counter 26 is supplied to the other inputs of these blocks. The outputs “O,” = of the first comparison unit 27 are connected to the inputs of the OR element 28, the output “>” of the first comparison unit 27, and the output “<” of the second comparison unit 29 connected to the inputs of the element And 30, and the outputs ">" and "=" with the inputs of the element OR 31.

The OR element 28 generates signals 5 corresponding to the estimate Νοω ^ Νίω. Element And 30 generates signals corresponding to the assessment Nom ^ Nom ^ Nom. The OR element 31 generates signals corresponding to the assessment Nom ^ Noui, which, according to the signal of the end of the 10th evaluation cycle from the output of the divider 24, are recorded in the register 32 and fed to the output of block 15.

Claims (1)

Claim 15 Device for receiving multi-position complex signals according to ed. St. No. 853819, characterized in that, in order to improve the quality of reception by providing control, an evaluation unit is introduced, consisting of a series-connected inverter, a sum of ² θ torus, error register, decoder and the first OR element, the output of which is connected to the first input of the first AND element whose output is connected to the first input of the divider counter ^ whose output 25 is connected to the first input of the second OR element, the output of which is connected to the first input of the summing counter, the outputs of which are connected to the inputs of the first and second blocks eniya, the first and second outputs of the second comparator 30 are connected to the inputs of a fourth OR gate and the third output - to a second input of the second AND gate, the outputs of the third and fourth members OR and the second AND gate are connected to respective inputs of evaluation of the register, whose outputs are 35 outputs of the evaluation unit, the corresponding output of the decoder is connected to the first input of the third element AND, the output of which is connected to the second input of the second element OR, and the input of the divider is ₄ Qa assessment, the corresponding input of the error register, the second inputs of the first and third elements AND are the input of the block evaluation and are connected to the output of the divider, the output of the divider of the evaluation unit is connected to the control input of the evaluation register and the second inputs of the totalizing counter and the counter-divider, the inverter inputs are the corresponding inputs of the block estimates and are connected to the outputs of the memory block, and the additional inputs of the adder, the first and second comparison blocks are inputs of the initial installation. Editor N. Tupitsa Order 1215/56 Compiled by N. Lazarev Tehred I. Veres Corrector M. Sharoshi Circulation 627 Subscription VNIIIPI of the State Committee for Inventions and Discoveries at the State Committee for Science and Technology 113035, Moscow, Zh-35, Raushskaya nab., D. 4/5 Production and Publishing Plant "Patent", Uzhhorod, st. Gagarina, 101