CN108173624B - Partial decoding polarization code serial offset decoding circuit and method thereof - Google Patents

Partial decoding polarization code serial offset decoding circuit and method thereof Download PDF

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CN108173624B
CN108173624B CN201810060361.3A CN201810060361A CN108173624B CN 108173624 B CN108173624 B CN 108173624B CN 201810060361 A CN201810060361 A CN 201810060361A CN 108173624 B CN108173624 B CN 108173624B
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CN108173624A (en
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杜高明
胡国庆
林青
张多利
宋宇鲲
王晓蕾
尹勇生
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Hefei Gongxin Xianxian Microelectronics Technology Co.,Ltd.
Hefei University of Technology
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract

The invention discloses a partial decoding polarization code serial offset decoding circuit and a method thereof, which is characterized by comprising the following steps: the device comprises a binary phase shift keying modulation module, a likelihood ratio calculation module and a bit hard decision module; the binary phase shift keying modulation module generates an initial likelihood ratio according to a receiving sequence; the likelihood ratio calculation module includes
Figure DDA0001555131470000011
The calculation stages are connected in turn in a recursion way, and the bit hard decision module carries out symbol decision according to a pair of likelihood ratios output by the final stage and outputs a decoding result. The invention only carries out paired decoding on at least one information bit of the adjacent channel, and can effectively reduce the number of likelihood ratio calculation units and the opening times while shortening the decoding period, thereby reducing the overall power consumption of the decoder and finally achieving the purpose of quick low power consumption of the whole decoder.

Description

Partial decoding polarization code serial offset decoding circuit and method thereof
Technical Field
The invention belongs to the technical field of network communication, and particularly relates to a partial decoding polar code serial offset decoding circuit and a partial decoding polar code serial offset decoding method.
Background
Polar Code is the latest in the field of coding at present, and is also the most concerned coding mode, and its proposal is a major breakthrough in the field of coding and is based on the channel polarization theory. The polar code has a deterministic construction method and is the only known channel coding method that can be strictly proven to "reach" the channel capacity. Compared with other coding modes, the lower complexity and the error correction performance capable of reaching the fragrance limit enable the polar code to be used as an important candidate of an error correction scheme in the field of next-generation digital communication and storage.
In the prior art, the decoding speed and power consumption of a Polar code serial offset decoding circuit are obviously improved, adjacent channels are basically required to be decoded in pairs by fixed bits, so that redundant calculation of a likelihood ratio calculation unit is brought, power consumption is increased, decoding delay is brought, the data throughput rate is Reduced, hardware overhead is increased, 2N-2 decoding cycles are required for completing one decoding, and the method is not applicable in occasions with higher communication real-time requirements, most of the Polar code serial offset decoding algorithms focus on how to accelerate the decoding speed, improve the data throughput rate or reduce the power consumption, and pay less attention to the performance influence of the two on the whole decoder, Liuxing, Zhang et al are 2013, IEEE international Conference DSP (digital signal Processing) published' A Stage-Reduced L-L adaptive decoding is used for decoding, decoding is still carried out by a Polar code serial offset decoding circuit, the decoding algorithm reduces the likelihood ratio by a large number of decoding cycles, the decoding speed is Reduced by the conventional decoding algorithm, the problem that the likelihood ratio of the Polar code serial offset decoding circuit is Reduced by 2N-2 decoding cycles, and the likelihood ratio is Reduced, and the problem that the decoding algorithm is still solved by the conventional serial offset decoding algorithm, and the problem that the likelihood ratio of the conventional decoding algorithm is Reduced by the simple decoding algorithm, and the likelihood ratio of the similar decoding algorithm, and the likelihood ratio of the similar decoding is increased by the similar decoding.
Disclosure of Invention
The invention provides a partial decoding polar code serial offset decoding circuit and a partial decoding polar code serial offset decoding method, aiming at solving the problem that the existing polar code serial offset decoding algorithm does not unify the decoding speed and the power consumption, and aiming at accelerating the decoding speed, improving the data throughput, reducing the hardware overhead, avoiding the redundant calculation of a likelihood ratio calculation unit, reducing the power consumption and further optimizing the overall decoding performance of the whole polar code serial decoder.
The technical scheme adopted by the invention to achieve the aim is as follows:
the invention relates to a partial decoding polarization code serial offset decoding circuit, which is characterized by comprising the following components: the device comprises a binary phase shift keying modulation module, a likelihood ratio calculation module and a bit hard decision module;
obtaining a fixed bit and an information bit in a transmission channel according to a channel polarization theory; the binary phase shift keying modulation module receives a code sequence { X ] in the transmission channel1,X2,…,Xi,…,XNCalculating the initial likelihood ratio of each code word
Figure GDA0002504675430000021
Wherein, XiDenotes the ith code, yiWhich represents the (i) th channel of the channel,
Figure GDA0002504675430000022
representing the ith code XiN is the code length of the polar code, i is 1,2, …, N;
the likelihood ratio calculation module receives the initial likelihood ratio
Figure GDA0002504675430000023
And in front of
Figure GDA0002504675430000024
The stage is recursively calculated to obtain
Figure GDA0002504675430000025
Two pairs of likelihood ratios for a stage; judgment of
Figure GDA0002504675430000026
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure GDA0002504675430000027
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure GDA0002504675430000028
Stage calculating corresponding likelihood ratio to obtain the second
Figure GDA0002504675430000029
A pair of likelihood ratios of the stages are output to the bit hard decision module;
the bit hard decision module receives the pair of likelihood ratios, performs symbol decision and outputs decoding bits; meanwhile, the likelihood ratio calculation module receives the decoding bit fed back by the bit hard decision module for the calculation of the likelihood ratio.
The invention relates to a partial decoding polarization code serial offset decoding method which is characterized by comprising the following steps:
step 1, obtaining a fixed bit and an information bit in a transmission channel according to a channel polarization theory;
step 2, coding sequence { X in the transmission channel1,X2,…,Xi,…,XNGet the receiving sequence (y) after modulating and adding additive white Gaussian noise1,y2,…,yi,…,yN}; then according to the receiving sequence y1,y2,…,yi,…,yNObtaining an initial likelihood ratio using equation (1)
Figure GDA00025046754300000210
Figure GDA00025046754300000211
In the formula (1), the reaction mixture is,2is the variance, yiFor the ith code XiThe code word after the interference is selected,
Figure GDA00025046754300000212
representing the ith code XiI is 1,2, …, N is the code length of the polar code;
step 3, preceding
Figure GDA00025046754300000213
Stage to initial likelihood ratio
Figure GDA00025046754300000214
Performing recursive calculation to obtain the second time in the current period
Figure GDA00025046754300000215
Two pairs of likelihood ratios for a stage;
step 4, judging
Figure GDA00025046754300000216
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure GDA00025046754300000217
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure GDA00025046754300000218
Stage calculating corresponding likelihood ratio to obtain the second
Figure GDA00025046754300000219
After a pair of likelihood ratios of the stages, step 5 is executed;
step 5, carrying out symbol decision processing on the pair of likelihood ratios to obtain decoding bits in the current period;
and 6, feeding the decoded bits back to the step 3 for calculating the likelihood ratio of the next period.
Compared with the prior art, the beneficial technical effects of the invention are as follows:
1. the invention relates to a polar code serial offset decoding circuit and a method thereof, which only carry out paired decoding on at least one information bit of an adjacent channel, if the second one is
Figure GDA0002504675430000031
Any pair of likelihood ratios of a stage is transmitted at a fixed bit, then at the second
Figure GDA0002504675430000032
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure GDA0002504675430000033
And in the stage, the corresponding likelihood ratio is calculated, and the likelihood ratio calculation structure is simplified and optimized, so that the complexity of likelihood ratio calculation is reduced.
2. The invention can replace the last stage of likelihood ratio calculation by using the bit hard decision module under the condition of not reducing the decoding accuracy, and only carries out the paired decoding on at least one information bit of the adjacent channel, thereby obviously accelerating the decoding speed and reducing the decoding period from the traditional 2N-2 to the approximate decoding speed
Figure GDA0002504675430000034
The real-time requirement of the decoder is enhanced, and the throughput rate and the decoding efficiency of data are improved.
3. The invention simplifies the likelihood ratio calculation structure on the basis of the traditional offset decoding algorithm, if a pair of bits of serial decoding are fixed bits, the likelihood ratio can not be calculated, and further, the calculation amount of a likelihood ratio calculation unit is effectively reduced, thereby reducing the power consumption of the whole decoder to a great extent.
4. The invention aims to reduce power consumption and accelerate decoding speed as design targets, and realizes the unification of speed and power consumption by using a partial decoding algorithm, thereby accelerating the decoding speed, reducing the power consumption and further improving the decoding performance of the whole decoder.
Drawings
FIG. 1 is a block diagram of a conventional serial cancellation decoding algorithm;
FIG. 2 is a block diagram of a portion of the decoding algorithm of the present invention;
fig. 3 is a schematic diagram of a bit hard decision module according to the present invention.
Detailed Description
In this embodiment, for convenience of description, it is assumed that the code length N of the polarization code is 8, the information bit a is (4,6,7,8) based on the channel polarization, and the fixed bit acThe fixed bit transmits bit '0', and the likelihood ratio calculation module is divided into 2 stages, stage 1 and stage 2, as shown in fig. 2; assuming that the coded code word sequence is V (00010111), binary phase shift keying modulation is performed on the coded sequence to obtain a modulated sequence S (+1+1+1-1+1-1-1-1), the modulated sequence is added with an average value mu (0), and the variance is V20.5 white additive Gaussian noise
Figure GDA0002504675430000035
Obtaining a reception sequence Y (-0.5+2.2+1.8-1.2-0.2-0.9-1.2-1), and calculating an initial likelihood ratio according to formula (1);
as shown in fig. 2, a partially decoded polar code serial cancellation decoding circuit includes: the device comprises a binary phase shift keying modulation module, a likelihood ratio calculation module and a bit hard decision module;
obtaining fixed bit A in transmission channel according to channel polarization theoryc(1,2,3,5) and information bit a ═ 4,6,7, 8; wherein the binary phase shift keying modulation module receives a code sequence { X ] in a transmission channel1,X2,…,Xi,…,XNAnd calculating the initial likelihood ratio of each code word according to the formula (1)
Figure GDA0002504675430000041
Wherein, XiDenotes the ith code, yiWhich represents the (i) th channel of the channel,
Figure GDA0002504675430000042
representing the ith code XiN is the code length of the polar code, i is 1,2, …, N;
likelihood ratio calculation module receives initial likelihood ratios
Figure GDA0002504675430000043
And in front of
Figure GDA0002504675430000044
The stage is recursively calculated to obtain
Figure GDA0002504675430000045
Two pairs of likelihood ratios for a stage; judgment of
Figure GDA0002504675430000046
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure GDA0002504675430000047
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure GDA0002504675430000048
Stage calculating corresponding likelihood ratio to obtain the second
Figure GDA0002504675430000049
A pair of likelihood ratios of the stages are output to the bit hard decision module; as shown in FIG. 2, u1u2…u8Indicating the code bit, the length of the polar code N is 8, and in the pair u1u2When decoding, since u1u2A pair of adjacent fixed bits, so that stage 2 does not calculate its corresponding likelihood ratio, and directly outputs the decoded bit
Figure GDA00025046754300000410
And decoding is done in pairs for u3u4，u5u6，u7u8Because the adjacent channel has at least one information bit, the corresponding likelihood ratio is calculated in the 2 nd stage, as shown in fig. 3, a pair of likelihood ratios obtained in the stage 2 is input to a bit hard decision module, the sign bits of the likelihood ratios are subjected to exclusive or operation to obtain odd decoded bits, and the sign bits with larger likelihood ratios are output as even decoded bits;
the bit hard decision module receives a pair of likelihood ratios and outputs decoding bits after symbol decision, the pair of likelihood ratios of the stage 2 is input into the bit hard decision module for symbol decision by using the decision function of the following formula, and if the likelihood ratios are not equal to the likelihood ratios
Figure GDA00025046754300000411
Decoding to 0, otherwise decoding to 1;
Figure GDA00025046754300000412
meanwhile, the likelihood ratio calculation module receives the decoding bit fed back by the bit hard decision module for the calculation of the likelihood ratio, as shown in fig. 2, the decoding output of the bit hard decision module
Figure GDA00025046754300000413
The feedback is input to the 4 g calculation units of phase 1,
Figure GDA00025046754300000414
the feedback is input to the 4 th, 8 th g calculation unit of stage 2.
In this embodiment, a partially decoded polar code serial cancellation decoding method is performed as follows:
step 1, obtaining a fixed bit and an information bit in a transmission channel according to a channel polarization theory;
step 2, coding sequence { X in transmission channel1,X2,…,Xi,…,XNIs carried outAfter the additive white Gaussian noise is modulated and added, a receiving sequence { y is obtained1,y2,…,yi,…,yN}; then according to the received sequence y1,y2,…,yi,…,yNObtaining an initial likelihood ratio using equation (1)
Figure GDA00025046754300000415
Figure GDA0002504675430000051
In the formula (1), the reaction mixture is,2is the variance, yiFor the ith code XiThe code word after the interference is selected,
Figure GDA0002504675430000052
representing the ith code XiI is 1,2, …, N is the code length of the polar code; it is assumed here that the coded codeword sequence is { 00010111 }, binary phase shift keying modulation is performed on the coded codeword to obtain a modulation sequence { +1+1+1-1+1-1-1-1}, the modulated sequence is added with a mean value μ ═ 0, and the variance is { 00010111 }, where2The received sequence Y is obtained, where the mean value μ is 0 and the variance is added20.5 additive white gaussian noise (taking noise samples)
Figure GDA0002504675430000053
Receiving the sequence Y (-0.5+2.2+1.8-1.2-0.2-0.9-1.2-1), and calculating an initial likelihood ratio according to formula (1);
step 3, preceding
Figure GDA0002504675430000054
Stage to initial likelihood ratio
Figure GDA0002504675430000055
Performing recursive calculation to obtain the second time in the current period
Figure GDA0002504675430000056
Two pairs of likelihood ratios for a stage;
step 4, judging
Figure GDA0002504675430000057
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure GDA0002504675430000058
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure GDA0002504675430000059
Stage calculating corresponding likelihood ratio to obtain the second
Figure GDA00025046754300000510
After a pair of likelihood ratios of the stages, step 5 is executed;
step 5, carrying out symbol decision processing on the pair of likelihood ratios to obtain decoding bits in the current period;
step 6, feeding back the decoded bits to step 3 for calculation of the next cycle likelihood ratio;
as shown in FIG. 2, the coding sequence is (x)1,x2,…x8) After binary phase shift keying modulation, the initial likelihood ratio is generated as
Figure GDA00025046754300000511
The upper right digits of likelihood ratio calculation units f and g indicate that the likelihood ratio calculation units f and g are started in the next clock period, the whole SC decoding structure is similar to DFT of a butterfly graph calculation sequence by FFT, 1), and when T is equal to 1, 4 groups of f factors of a stage 1 receive an initial likelihood ratio; 2) when T is equal to 2, 2 groups of g factors of the stage 2 receive the output result of T is equal to 1, the obtained 2 calculated values are transmitted to a bit hard decision module, and decoding is carried out
Figure GDA00025046754300000512
3) When T is 3, 4 groups of g factors of the stage 1 receive an initial likelihood ratio; 4) when T is 4, 2 groups of f factors of the phase 2 receive the output result of T is 3, and the obtained 2 calculated values are transmitted to the bit hardDecision module, decoding
Figure GDA00025046754300000513
5) When T is 5, 2 groups of g factors of the stage 2 receive the output result of T is 3, the obtained 2 calculated values are transmitted to a bit hard decision module, and decoding is carried out
Figure GDA00025046754300000514
Figure GDA00025046754300000515
Figure GDA00025046754300000516
In the formula (3) i.e. f,
Figure GDA0002504675430000061
in order to receive the sequence of the data,
Figure GDA0002504675430000062
and
Figure GDA0002504675430000063
for receiving a sequence
Figure GDA0002504675430000064
The upper part and the lower part of the frame,
Figure GDA0002504675430000065
subvectors (u) representing odd indicesk:1≤k≤j；k odd)，
Figure GDA0002504675430000066
Sub-vector (u) representing even indexkK is more than or equal to 1 and less than or equal to j, k even), sgn represents a sign function, a sign '⊕' represents exclusive-or operation, min represents the minimum value, '|' represents the absolute value, in formula (4), i.e. g,
Figure GDA0002504675430000067
is shown to haveThe decoded bits.
In this embodiment, assuming that the length N of the polar code is 8, a polar code serial cancellation decoding algorithm of partial decoding is implemented by Verilog HD L, and compared with a conventional serial cancellation decoding algorithm and a decoding algorithm of likelihood ratio reduction, as shown in table 1;
TABLE 1 comparison of performance of three decoding algorithms
Figure GDA0002504675430000068
As shown in fig. 1, for the conventional serial cancellation decoding algorithm, the likelihood ratio calculation is divided into three stages, i.e., stage 1, stage 2, and stage3, 14 cycles are required for completing one decoding, the calculation unit is started 24 times, and the calculation condition of the likelihood ratio calculation unit in each cycle is shown in table 2;
TABLE 28-Bit conventional Serial offset decoding period
Figure GDA0002504675430000069
Figure GDA0002504675430000071
As shown in table 3, for the reduced-order decoding algorithm, the working conditions of the likelihood ratio calculation unit in each period are listed, 6 periods are required for completing one decoding, and the calculation unit is started 16 times;
TABLE 38-Bit reduced-order successive cancellation decoding period
Figure GDA0002504675430000072
As shown in fig. 2, the system structure diagram of partial decoding only performs pair-wise decoding on at least one information bit of an adjacent channel, in short, if the adjacent channel is a pair of fixed bits, the decoding is not performed; as shown in table 4, 5 cycles are required for completing one decoding by a partial decoding algorithm, and the computing unit is turned on 14 times, so that compared with the conventional serial cancellation decoding, the hardware overhead of 10 likelihood ratio computing units is reduced, the decoding cycle is reduced to 5 cycles from the conventional 14 cycles, and the data throughput is improved by about 2.3 times.
TABLE 48-Bit partial serial cancellation decoding period
Figure GDA0002504675430000073
As shown in table 5, in this experiment, a Polar code serial cancellation decoding algorithm of partial decoding and a recurrent article "a Stage-Reduced L ow-L inherent subsequent decoding decoder for Polar Codes" first-order serial cancellation decoding algorithm are implemented by Verilog HD L, and the asic employs a 180nm process, where the code length N is 8, the fixed bit number K is 4, and the code rate R is 0.5, the resource consumption of the partial decoder is Reduced by about 16% compared with the Reduced-order decoder, and the power consumption is Reduced by about 6%.
Table 5 partial decoding compares the results of the reduced order decoding measurements with N8, K4, and R0.5
Figure GDA0002504675430000081

Claims (2)

1. A partially decoded polar code serial cancellation decoding circuit, comprising: the device comprises a binary phase shift keying modulation module, a likelihood ratio calculation module and a bit hard decision module;
obtaining a fixed bit and an information bit in a transmission channel according to a channel polarization theory; the binary phase shift keying modulation module receives a code sequence { X ] in the transmission channel1,X2,…,Xi,…,XNCalculating the initial likelihood ratio of each code word
Figure FDA0002504675420000011
Wherein, XiDenotes the ith code, yiWhich represents the (i) th channel of the channel,
Figure FDA0002504675420000012
representing the ith code XiN is the code length of the polar code, i is 1,2, …, N;
the likelihood ratio calculation module receives the initial likelihood ratio
Figure FDA0002504675420000013
And in front of
Figure FDA0002504675420000014
The stage is recursively calculated to obtain
Figure FDA0002504675420000015
Two pairs of likelihood ratios for a stage; judgment of
Figure FDA0002504675420000016
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure FDA0002504675420000017
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure FDA0002504675420000018
Stage calculating corresponding likelihood ratio to obtain the second
Figure FDA0002504675420000019
A pair of likelihood ratios of the stages are output to the bit hard decision module;
the bit hard decision module receives the pair of likelihood ratios, performs symbol decision and outputs decoding bits; meanwhile, the likelihood ratio calculation module receives the decoding bit fed back by the bit hard decision module for the calculation of the likelihood ratio.
2. A partial decoding polarization code serial offset decoding method is characterized by comprising the following steps:
step 1, obtaining a fixed bit and an information bit in a transmission channel according to a channel polarization theory;
step 2, coding sequence { X in the transmission channel1,X2,…,Xi,…,XNGet the receiving sequence (y) after modulating and adding additive white Gaussian noise1,y2,…,yi,…,yN}; then according to the receiving sequence y1,y2,…,yi,…,yNObtaining an initial likelihood ratio using equation (1)
Figure FDA00025046754200000110
Figure FDA00025046754200000111
In the formula (1), the reaction mixture is,2is the variance, yiFor the ith code XiThe code word after the interference is selected,
Figure FDA00025046754200000112
representing the ith code XiI is 1,2, …, N is the code length of the polar code;
step 3, preceding
Figure FDA00025046754200000113
Stage to initial likelihood ratio
Figure FDA00025046754200000114
Performing recursive calculation to obtain the second time in the current period
Figure FDA00025046754200000115
Two pairs of likelihood ratios for a stage;
step 4, judging
Figure FDA00025046754200000116
Whether any pair of likelihood ratios of the stages are transmitted at fixed bit positions, if so, at the second stage
Figure FDA00025046754200000117
Stage does not calculate corresponding likelihood ratio, and directly outputs fixed bit; otherwise, in the second
Figure FDA00025046754200000118
Stage calculating corresponding likelihood ratio to obtain the second
Figure FDA00025046754200000119
After a pair of likelihood ratios of the stages, step 5 is executed;
step 5, carrying out symbol decision processing on the pair of likelihood ratios to obtain decoding bits in the current period;
and 6, feeding the decoded bits back to the step 3 for calculating the likelihood ratio of the next period.
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