FI82871C - KRETSANORDNING FOER FOERVERKLIGANDE AV EN VITERBI-ALGORITM. - Google Patents

Abstract

The invention concerns a circuitry implementing the Viterbi algorithm at such a trellis at which each state may be reached along two alternative paths. The states of the bits of a defined time interval are processed utilizing the inventive circuitry in serial form for indicating the symbol including one bit and/or several bits. The invention may be applied, for instance, in the GSM mobile telephone, in which, by the aid of the invention, the signal processing circuits may be saved significantly.

Description

1 82871

Circuit arrangement implementing the Viterbi algorithm

The invention relates to a circuit arrangement implementing the Viterbi algorithm according to the preamble of claim 1.

The Viterbi algorithm is an algorithm commonly used to decode convolutional codes. The Viterbi algorithm is used in receivers of digital transmission systems, for example in the pan-European digital mobile telephone system (GSM, Groupe Special Mobile), where digital information transmitted on a radio path is coded on a channel-by-channel basis (convolutional coding) and on the transmission chain (transmitter, radio channel which can be treated as inadvertent analog convolutional coding. The data signal encoded on the receiving side must be expressed so that the most probable transmitted bit string is found. The Viterbi algorithm can be used for this decoding, both for the detection of the receiver bits 20, in which the unintentional analog convolutional code generated by the transmission chain interaction is decoded, and for the decoding of the channel (convolutional coding).

Figure 1 shows the Viterbi-Trellis coding known per se on the basis of the present invention and its operation. Each received bit (BIT *, BITjc + i) is associated with 16 possible states STATES. Each state is associated with a cumulative value, CUM, which describes how likely or "good" the path is from the beginning of the bit pattern, i.e., the specified time interval, to that state. Figure 1 also shows (within the trellis used herein) the allowable transitions from one state to another. Each transition is associated with a transition value TRANS that defines the "goodness" of each transition. Each space in this trellis can be accessed along two alternative 35 routes. Adding the cumulative values CUM * of the output state of the previous bit, BIT *, and the transition values TRANS *, we obtain the "goodness value" CUM * + i for each possible state of the next bit, BIT * + i, from which the "goodness" of the 2 82871 bit path can be derived from the beginning . Since there can be 16 states and two paths lead to each state, there can be 32 transition values j.

Figure 2 illustrates the states associated with each bit DET.BIT: the previous state OLD STATE and the new state NEW STATE, to which the above-mentioned CUM values are associated, and between which bit-specific possible transitions are described by the TRANS values.

10

By comparing the "goodness" of the two routes coming to each state, the better of these can be chosen. The sum of the cumulative value CUM * of the output state of the selected route and the transition value TRANS * is stored as the cum-15 value of the state of the next, newer bit BIT * + i. For each bit, 16 states i must be computed, the cumulative values of which states CUM * (i) are stored in the Trace Back (TB) table.

Conventionally, the Viterbi algorithm described above is implemented with parallel arranged circuits (e.g., one circuit for each bit state, in this case 16 parallel circuits). A large number of circuits raises equipment costs. In addition, for example, in a GSM mobile phone, a large number of components increase power consumption.

25

The object of the invention is to eliminate or reduce the above-mentioned disadvantages.

The task is solved by a circuit arrangement according to the characterizing part 30 of claim 1.

By processing the information related to each possible state of the bit under consideration in a serial form, i.e. in succession, the circuit arrangement can be made very simple.

35 The processing of the Viterbi algorithm described above is performed in the same way for each state. For each bit, 16 states are counted in succession, and the associated values are stored in the return path table. Once all the bits in the 3,82871 time slots in question have been processed, a return route search is performed based on the stored values, thereby probably following the best route from end to beginning. This indicates each bit of the time slot and / or the 5 symbols associated with the bits.

The same circuit arrangement can be used, for example, in a GSM mobile phone to detect the bit string of the receiver, and in addition it can perform decoding (channel decoding) of the channel-specific coding. The advantage of a simple implementation is reduced power consumption, which is a significant advantage, for example, in a battery-powered GSM mobile phone. The circuit arrangement according to the invention can be implemented as an integrated circuit, e.g. a VLSI circuit.

15

According to the principles of the invention, it is also possible to implement any other Viterbi algorithm using the trellis of Figure 1.

The invention will now be described with reference to the figures of the drawing, in which: Figure 1 shows the operation of a known Viterbi-Trellis algorithm in tabular form; Fig. 2 shows, in a simplified manner, the known detection principle of the bit to be examined by means of values associated with two states; Fig. 3 shows a block diagram of a circuit arrangement according to the invention implemented in series with a Viterbi algorithm; and Fig. 4 shows a basic block diagram of retrieving the return route.

Figure 3 shows a circuit arrangement according to the invention, which can be applied, for example, in the detection and / or channel decoding of bits received in a GSM mobile telephone. The input data for the circuit arrangement is 32 transition values TRANS (j), TRANS (j + 1) associated with one bit BIT (k + 1) 4 82871, which are transferred to the transition value table TT. The cumulative values CUM (i) of the previous bit are stored in a table CT (CUM Table) from which they are derived into the summers ADD; to the second 5 adder ADD via the delay circuit L (Latch). In the adder, the sum of the transition values TRANS and the cumulative values CUM associated with each state is performed. The amounts thus obtained are compared in the subtractor SUB. By means of the most significant bit MSB of the subtraction, the selection member 10 SEL selects the larger amount as the new cumulative value NEW, which is stored in the table of cumulative values CT. The result of the subtraction DF (Difference), scaled to the desired number of bits, is stored in the trace back table TB (Trace Back Table).

15

All states associated with a given bit are calculated in the same way sequentially, i.e. in series, and the results are stored in tables CT, TB. When the calculation of one bit is completed, the transition values associated with the next bit are read, and the same sequence is restarted. The calculation is repeated for all bits of the specified time interval. ("Time interval" here can mean e.g. a GSM system frame with 148 bits).

25 When all the bits of the interval have been processed, a return route search is performed. Figure 4 shows a schematic block diagram of a circuit arrangement implementing this step. The "best" route, i.e. the route description, is read from Table TB (Figure 3). The top bit 30 MSB (T) (most significant bit) of the difference DF stored in the table TB corresponds to the detected bit, and it indicates which path according to the trellis reaches the state of the previous bit. When this highest bit MSB (T) is summed to the value of the state shifted to the left, the value of the next state LSB, i.e. the four least significant 35 bits, is obtained by going back. The LSB value indicates the value of the state following the address location (backwards) of the return route memory. In Fig. 4, the circuit L is a delay circuit, and the circuit SL1 (Shift Left One) shifts the current value by one bit to the left.

Il 5 82871 This is done for each bit of the time slot until the entire bit string of the time slot is indicated. After that, the processing of the bits of the next time slot is started.

Claims (3)

6 82871 1. A circuit arrangement implementing the Viterbi algorithm with a trellis in which each state can be terminated along two alternative paths, adding to the cumulative value of the output state of the received bit 5 (BIT *) (CUM * (i)) a transition value corresponding to a given transition (TRANS * (j)) and thus obtaining for each possible state of the next bit (BIT * + x) a cumulative value (CUMic + i (i)) from which the bit path goodness from the beginning of the time slot can be derived, characterized in that the bit states of the defined time slot are serially processed by the circuit arrangement / or to indicate a symbol formed by several bits. A circuit arrangement according to claim 1, characterized in that it comprises circuits by which: a) for each bit (BIT *) in the summing circuits (ADD) the cumulative values (CUM (i)) and bits (BIT *) of the respective states are formed; BIT * + (i) the sum of the transition values (TRANS *) of the changes between; 20 b) comparing in the subtraction circuit (SUB) the two sum values of each state; c) storing the result of the comparison (DF) in the return route table (TB); and d) selecting a new cumulative value (NEW) of the bit processed by the selection circuit (SEL), which is stored in a table of cumulative values (CT), repeating the operation (steps a to d) for each of the 16 possible states of the bit, and the operation sequence is repeated for each bit of the interval to determine the return path. The circuit arrangement according to claim 2, characterized in that it further comprises: e) a return path assignment circuit, wherein on the basis of the bit-specific information (MSB (T)) read from the return path table, a memory I! 7 82871 a location address (LSB) from which the most probable value of the current bit or symbol can be read, in which case the bits or symbols of the time slot are expressed in time from the last. 5