SU1462351A1 - Device for processing data - Google Patents

Abstract

The invention relates to computing and can be used to detect and determine the direction to a radiation source of signals. The aim of the invention is to expand the functionality by receiving signals from the radiation pattern of an antenna array, on the receiver inputs of which sound pressure and pressure gradient signals are formed in three orthogonal coordinates. The device contains a reception unit 1, an analog-digital converter 2, a switch 3, a buffer memory block 4, a multiplier 5, a wired controller adder 6, a RAM block 7, a accumulator 8, a switch 9, a coefficient memory block 10, a switch 11, block 12 of the memory of the inputs of the delays, adder 13, block 14 of the in- vert, counter 15 of the current sample, block 16 of the control. 3 il. (L

Description

FIG. one

The invention relates to computing technology and can be used to solve problems of detecting and determining the direction to a source of radiation of signals.

The purpose of the invention is to expand the functionality of the device by receiving signals from the radiation pattern of the antenna array, at the outputs of receivers that generate sound pressure signals and, the pressure gradient along three orthogonal coordinates,

FIG. 1 shows the circuit of the device; FIG. 2 is a control block diagram; in fig. 3 - temporary work diagrams.

The device contains a reception unit 1, an analog-digital converter (ADC) 2, a switch 3, a buffer memory block 4, a multiplier 5, accumulating adder 6, a random-access memory unit 7, accumulating adder 8, a switch 9, coefficient block 10 , switch 11, delay codes memory block 12, adder 13, inversion block 14, current sample counter 15, control block 16, clock pulse generator 17, counter 18, switch 19, channel counter 20, switch 21, coefficient counter 22, triggers 23 and 24, the decoder 25, the element And 26, shaper 27 right triggers 28 and 29, a step counter 30, a group of 31 OR elements, a counter 32 directions, a switch 33, a square pulse shaper 34, a group of 35 OR elements, inputs and outputs 36-41.

The device works as follows.

The signals from the outputs of the receivers of the artificial grating (P is the sound pressure value at the receiver V ,,, Vy, the three orthogonal components of the receiver pressure gradient, i 1 ... M) are fed to the inputs of the A / D converter 2, where they are digitized and digitized. . The formation of signals from the radiation pattern of the antenna array with phase-vector elements is carried out in three stages.

The first stage is performed when the current sample pulse arrives from the output of the A / D converter 2 to the input of control unit 16 and to the input of counter 15, which is then transferred to the next state. Digital samples of signals from the output of the ADC are successively fed to the information input of switch 3, and from its output are recorded in block 4. After recording four samples from the last phase-array antenna receiver, the device proceeds to perform the second processing stage.

During the second stage, the signals are converted according to the expressions

 X, V v

v, -

 V, -,

 Vx, Sin I / + Vy; Cos

 V ,,, - sin - Vx.-cos C; VJ (sin c- + V cosM)

M

 V

i: h (j)

V

vf

RDP - j).

0 5 | where V, -, 5 0

.i

Vl

0

p.

one

to

Z d

- sampling of pressure gradient signals along the axis X, Y, Z from the receiver, i 1 ... M;

- selection of pressure signal i of the receiver i

-the length of the impulse response of the differentiator;

Cf is the horizontal angle $ V is the vertical angle; h (j) are the coefficients of the impulse response of the differentiator;

BCw) - cardioid characteristic. Initially, the directivity pattern of the individual phase-vector receivers is formed by rotating the three-orthogonal components of the pressure gradient at angles / and i, given at the input of the device. This operation is performed in nine cycles.

During the first cycle, block 4 reads KONOioHeHTa V, which is written into the multiplier multiplier 5. Simultaneously, the coefficient memory 10 is counted from the value of the function sinl, which is fed through switch 11 to the input of the multiplier 5. The result of multiplying from the multiplier 5 output is entered into the previously zero accumulated adder 6.

During the second clock cycle from blocks 4 and 10, the component Vy is read out respectively, and the value of the function cos C is similar to the first clock and the result of multiplication from the output of multiplier 5 is summed with the result of multiplying the first clock in accumulator 6.

During the third clock cycle, the transformed component V is transmitted through switch 3 and is written to the cell of unit 4, where the component code V y, was previously located.

During the fourth cycle, the value of the function sinif is read from the coefficient memory block 10, which through the switch 11 enters the input of the multiplier 5, where it is written to the multiplier register. The multiply register 5 at this time contains the code of the component V, recorded during the second cycle, the result of the multiplication is again entered into the preset zero accumulator 6.

During the fifth cycle, V is multiplied by costf, and the result of the multiplication is subtracted from the code in adder 6,

During the sixth cycle, the transformed component V (,, is written into the cell of block 4, in which the code of the component V,,

During the seventh and eighth cycles, v is calculated, which is performed similarly to the first two cycles, the only difference being that the values of sinti and cost are received from the coefficient memory unit 10, and the component codes are read from block 4.

V x,, V ,,.

During the ninth cycle, the code of the transformed component V, is stored in the first cell of the RAM block 7. At the first address input of the RAM block 7, the channel number code is sent, and the second address input is the current sample code received from the code of the summer 13, the second input of which receives zero information from the output of the memory block 12 of the delay codes and from the outputs of block 14.

During the next two clock cycles, the value of B is determined. During the tenth clock cycle, from block 4, the converted component V is read, which is written into the multiplicative register 5, and during the eleventh clock, from block 4, the converted component Vy is read, which through switch 11 is written to the register multiplier, the result of the multiplication is recorded in the accumulating adder 6, which was previously set to zero in the first stage of processing.

During the twelfth cycle, the code from the output of accumulating adder 6 is recorded in the second cell of the RAM 7, from the output of which is fed to the input of accumulating adder 8, where it is summed up with the previous result.

Starting from the thirteenth cycle, the device performs K cycles (K is the length of the impulse response of the differentiator), during which the amplitude-frequency characteristic is corrected and the phase shift by 90 ° of the sound pressure signals P. The differentiator's tacts are executed as follows. From the output 41 of the control block 16 to the input of the coefficient memory block 10 a level 1 is received which selects a region in the coefficient memory in which the coefficients of the differentiator impulse response are located, the same level 1 goes to the control input of the switch 9, connecting the output 40 of the block 16 controls through this switch to the input of the coefficient memory block 10. Output 39 of block 16 receives a channel address code and address codes for reading K samples of the sound pressure signal P of the first receiver. From the output of block 4, samples P are recorded in the register of multiplicative multiplier 5. At the same time, the values of the coefficients of the impulse response of the differentiator are fed to the input of the multiplier register. At the end of each clock cycle, the result of the multiplication is entered into accumulative adder 6, which is zeroed before the first differentiation cycle. After completing the differentiation cycles K, the converted signal sample P is entered into the second cell of the first roll of the RAM block 7. A code equal to the sum of the counter code 15 and the K / 2-1 code is fed to the address input of this block from the output of the adder 13. Sound pressure signal sample P is shifted to offset the delay of signals during differentiation. To generate a K / 2 code - 1, the input of block 14 from the output of block 16 receives level 1, the null information coming from the output of block 12 is converted at the output of block 14 into a code consisting of logical units. After entering the sample R. on the address

the input of block 4 from the output 39 of the control unit receives the address code of the next channel and the conversion cycles of the four samples V, V are flowing,

processing as follows. The sampling impulse arriving at the input of block 16 sets the triggers 23 and 24 to one state. The level from the output of the trigger 23 permits the operation of the generator 17, which produces a series of clock pulses at the input of the counter 18, at 10 its output sequentially. codes with which four components of the signals of each phase-vector receiver are recorded .-- The address code from the counter 18 output

V-J, P of the next channel, which will produce a group of 35 IL elements, will be performed in the same way as before. After the conversion of the samples of the last channel is completed, the device proceeds to the third stage of processing the samples of the signals of the antenna array. 20

During the execution of the third stage of processing, the forging of samples of signals along the radiation pattern is carried out. The step is performed as follows. From release 36 25. the control unit to blocks 12 and 7 receives the address code of the channel, and the code of the direction number. In block 12, the relative channel delay codes for different directions of arrival of signals are located. At the output of the adder 13, a code is formed, the equal sum of the code at the output of the counter 15 and the output code at the output of block 12. According to this code, one sample from the array of signal samples of this channel is read from block 7 of the operational g memory. The code from the output of this block is fed to the input of accumulating adder 8, which is communicating before forming a signal in each direction. After reading the samples of the sound pressure signal P, the converted component of the oscillatory velocity 45 V is read for each channel. After reading the two samples of the signals of the last channel, a total P + + V signal is generated in this direction at the output of the device and the device proceeds to form a signal along the next beam of the radiation pattern. After the formation of a signal on the last beam of the radiation pattern, the device enters gg into the standby mode before the next sampling pulse arrives.

Control unit 16 generates control signals for the three steps.

returns to output 39 of the control unit. The signal from the output of the second bit of the counter 18 is fed through the switch 19 to the input of the Counter of 20 channels and sets it to the next state by the falling edge. The output 39 of block 16 receives the address code of the next channel and the next four components are recorded in block 4. After recording the samples of the last channel, the signal from the output of the highest row of counter 20 sets a flip-flop 24 to the O state, which leads to set to the single trigger state 28. At the same time, the signal from the high bit output of the channel counter 20 through the switch 21 sets the next front to the next state the counter 22, the code from the output of which goes to the output 39 of the block

The generation of the control signals for the second processing step is performed as follows. Uro

The first one from the output of the trigger 28 is transferred to the installation input of the counter 30 and translates it into the counting mode. The generation of control signals for converting the components of one channel is explained by the time diagrams shown in FIG. 3. One of the sections of the timing diagram corresponds to the operation of rotating the samples of the three components of the gradient Vn, V ,,, Vj, and the other to differentiating the sound pressure signal samples P, The output code of the meter 30 is fed to the input section. torus 25, at the output of which levels 1 appear, allowing the formation of control signals for the execution of a given clock cycle of the second stage. The first output of the decoder 25 generates an address code for

23516

processing as follows. The sampling pulse, which arrives at the input of the block 16, sets the triggers 23 and 24 to one state. The level from the output of the trigger 23 permits the operation of the generator 17, which produces a series of clock pulses at the input of the counter 18, at its 10 output successively The codes used to record the four components of the signals of each phase-vector receiver. The address code from the output of the counter 18 through the group 35 of the elements of the IZH arrives at the output 39 of the control unit. The signal from the output of the second bit of the counter 18 goes through the switch 19 to the input of the Counter of 20 channels and sets it to the next state with a falling edge. The output 39 of block 16 receives the address code of the next channel and the next four components are recorded in block 4. After recording the samples of the last channel, the signal from the output of the high bit of the counter 20 sets the flip-flop 24 to the O state, which causes the unit to become one. trigger status 28. At the same time, the signal from the high bit output of the channel 20 counter through the switch 21 sets the next edge to the next state of the counter 22, the code from the output of which goes to the output 39 of unit 16

The generation of the control signals for the second processing step is performed as follows. Level 1 from the trigger output 28 post pa.et on the installation input of the counter 30 and translates it into the counting mode. The generation of control signals for converting the components of one channel is illustrated by the timing diagrams in FIG. 3. One of the sections of the time diagrams corresponds to the operation of rotating the samples of three components of the pressure gradient Vx, V ,,, Vj, and the other to the differentiation of the samples of the sound pressure signal P, the output code of the counter 30 is fed to the input of the section 25, the output of which levels 1 appear, allowing the generation of control signals for the execution of a given clock cycle of the second stage. The first output of the decoder 25 generates an address code for

reading and writing information of four samples of each channel from block 4, which goes through a group of 35 elements OR to output 39 of block 16. The signal. from the second output of the decoder, which also goes to output 3.9, controls the record-read mode of information of block 4. The code from the third output of the decoder 25 allows the generation of clock pulses for recording information into accumulating adder 6 and zeroing it and recording the information in register 10

citator. The code from the eighth output of the decoder 25 is fed through the switch 33 to the output 37 of the block 16 and is used to record information in the accumulating adder 8 when receiving the cardioid pattern. After the completion of T, the counter 30 is zeroed. The signal from the high-order output of this counter through the switch 19 takes the trailing edge of the counter 20 to the next state, and the shaping of the control signals is carried out

multiplier 5. Formation of impulse-15 To convert four samples

35

The clock is carried out by the driver 27 along the edges of the pulses received from the clock generator 17 in accordance with the timing diagrams in FIG. 3. Recording and zeroing pulses are received from the output of driver 27 at output 38 of block 16. Code from the fourth output of decoder 25 allows clock pulses from the output of generator 25 to pass through element 26 and switch 21 to counter 22 input during execution . of differentiation. This counter counts by; module K, therefore, upon receipt of the K-th tWe pulse, the counter is reset. The code from the output of counter 22 is fed to output 39 of block 16 and is used to read the K samples of the signal P over this channel. The code from the fifth output of the decoder 25 is fed to the output 37 of block 16 and is used to control the writing of the converted components to the RAM block 7. At Q, the same output generates level 1 when writing the converted sample P, which enters the input of block 14. At the sixth code of the decoder 25, an address code is generated for 45 storing the transformed components into the corresponding two cells of the operational memory 7. This code through the OR elements of group 31 enters output 36 of block 16. Code from the seventh output of decoder 25 enters output 46 of block 16 and controls the transmission of information through switches 11 and 9, and also selects areas of coefficient multiplier 10, The gg of which contains the values of the functions of the sine and the squint of the angles of rotation. gradient components and the impulse response coefficients of the differentials of the next receiver are similar to that described. When generating the control signals of the last channel, the signal from the output of the higher-order row of counter 20 is trailed by trigger 28, which then sets trigger 29 to the single state.

I

50

The formation of the control signal of the third stage of processing is carried out as follows. The input of the counter 20 comes through the switch 19 from the output of the counter 18 pulses, which switch the setter 20 to the next state. The codes from the output of the counter 20 arrive at the output 36 of the block 16. The same code receives the code from the outputs of the counter bits 32 and the IZ elements of group 31 the code from the output of the first bit of the counter 32 which is used to control the reading of samples P or v. The counter 32 switches to the next state on the falling edge of the signal from the output of the higher bit of the counter 20. The write pulses for the accumulating adder 8 come from the output of the switch 33 to the output 37 of the block 16. After forming the total signal P + V in this direction on the falling edge of the signal from the output of the first bit of the counter 32, information tracking pulses and zeroing pulses on the accumulating adder 8 are formed using the imaging unit 34. When forming the signal in the last direction on the falling edge of the signal from the output For the last bit of counter 32, trigger 23 is triggered and trigger 29 by control block 16 stops the generation of control signals until the next start pulse.

citator. The code from the eighth output of the decoder 25 is fed through the switch 33 to the output 37 of the block 16 and is used to write information to the accumulating adder 8 when receiving the cardioid pattern. After the clocks have been executed, the counter 30 is zeroed. The signal from the high-order output of this counter through the switch 19 takes the trailing edge of the counter 20 to the next state, and the shaping of the control signals is carried out

To convert four samples

To convert four samples

signals of the next receiver as described. When generating the control signals of the last channel, the signal from the output of the most significant bit of the counter 20 trailing edge resets the trigger 28, which sets the trigger 29 to one state.

I

The generation of control signals of the third stage of processing is performed as follows. The input of the counter 20 is received via the switch 19 from the output of the counter 18 pulses, which switch the set 20 to the next state. Codes from the output of counter 20 arrive at output 36 of block 16. At the same code comes the code from the outputs of the bits of counter 32 and through the elements of the ILI group 31 the code from the output of the first bit of counter 32, which is used to control the reading of samples P or v. The counter 32 switches to the next state on the falling edge of the signal from the high bit output of the counter 20. Recording pulses for the accumulating adder 8 are output from the switch 33 to the output 37 of block 16. After forming the total signal P + V in this direction along the falling edge of the signal from the output of the first bit of counter 32, information tracking pulses and zeroing pulses of accumulating adder 8 are generated using shaper 34. When generating a signal in the last direction on the falling edge of the signal the most recent discharge of the counter 32 are reset flip-flop 23 and flip-flop 29 and the control unit 16 stops generating control signals until the next start pulse.

Claims (2)

1. A device for processing data when generating a grid antenna diagram of an antenna array that contains a receiving unit whose output is connected to an information input of an analog-digital converter, the READY output of which is connected to the counting input of the current sample counter and the start input of the control unit whose first output connected to the address input of the memory of the delay codes and the first address input of the RAM, the output of which is connected to the information input of the first accumulating adder, the output to The device is the output, the second address input of the RAM block is connected to the output of the adder, the input of the first addend of which is connected to the output of the current sample counter, characterized in that, in order to extend the functionality by receiving signals through the beams of the radiation pattern the antenna array, at the outputs of the receivers of which the sound pressure and pressure gradient signals are formed in three orthogonal coordinates, the first, second, third switches, the buffer memory block are entered into it and, a multiplier, a second accumulating adder, an inversion unit, a coefficient memory unit, wherein the information output of the analog-digital converter is connected to the first information input of the first switch, the second information input of which is connected to the information input of the main memory unit and to the output of the second accumulating adder , the second output of the control unit is connected to the enabling input of the inverting unit, to the write input of the first accumulating adder and to the write / read input of the operating unit The second memory, the control inputs of the second accumulating adder and the multiplier are connected to the third control block, the fourth output of which is connected to the input of the operation of the buffer memory block, the output of which is connected to the first information input of the second switch and to the input of the multiplicand multiplexer five 0 0 5 About 5 0 5 which is connected to the information input of the second accumulating adder, the multiplier multiplier input is connected to the output of the second switch, the second information input of which is connected to the output of the coefficient memory block, the information input of which is connected to the output of the third switch, the first information input of which is the device input, the second information input the input is connected to the fiveth output of the control unit, the sixth output of which is connected to the control inputs of the first, second and third switches and to the input the operation of the coefficient memory block operation, the output of the first switch is connected to the information input of the buffer memory block, the first output of the memory block of delay codes and the output of the inverting block are connected to the inputs of the second and third eMbJx adder, respectively, the second output of the memory block delay codes are connected to the information input of the inversion unit, 2. The device according to claim 1, characterized in that the control unit contains four flip-flops, a counter, switches, a channel counter, a coefficient counter, a step counter, a decoder, a direction counter, two groups of PW elements, an And element, two square pulse formers and clock generator, the start input of which is connected to the output of the first trigger, and the output is connected to the counting input of the counter, to the counting input of the step counter g, to the first input of the And element and to the clock input of the first fortir of rectangular pulses, the output cat pogo is the third output of the block, the single inputs of the first and second triggers are connected to the start input of the block, the output of the second trigger is connected to the single input of the third trigger, to the control input of the first switch and to the sixth output of the block, the outputs of the counter bits are connected to the first inputs of the elements OR of the first group, the outputs of which are connected to the fourth output of the block, the second inputs of the elements OR of the first group are connected to the first output of the decoder, the second output of which is connected to the fourth output of the block, the third output d the decoder is connected to the control input of the first square pulse generator, the fourth decoder riser is connected to the second input of the element I, the output of which is connected to the first information input of the first switch, the output of which is connected to the counting input of the coefficient counter, the output of which is connected to the fourth output of the unit , the output of the second discharge of the counter is connected to the first information inputs of the second and third switches, the output of the second switch is connected to the counting input of the channel counter, the output The bits of which are connected to the first and fourth outputs of the block, the output of the higher bit of the channel counter is connected to the second information input of the first switch, to the zero inputs of the second and third flip-flops and to the counter input of the direction counter, the output of the last bit of which is connected to the cool inputs of the first and the fourth trigger, the output of the third trigger is connected to the control inputs of the second switch and the decoder, to the single input of the fourth trigger and to the the output of the step counter, the output of the fourth trigger is connected to the installation input of the direction counter and the second information input of the third switch, the output of which is connected to the second output of the block, the bit outputs of the step counter are connected to the information input of the decoder and the fifth output of the block, the output of the higher bit Yes, the step counter is connected to the second information input of the second switch, the fifth output of the decoder is connected to the second output of the block, the sixth output is connected to the first inputs of the OR elements of the second group, the output which ports are connected to the first output of the block, the second inputs of the OR elements of the second group and the input of the second square pulse generator are connected to the output of the first discharge of the direction counter, the bit outputs of which are connected to the first output of the block, the output of the second square pulse generator is connected to the second output unit, the seventh output of the decoder is connected to the sixth output of the unit, the eighth output is connected to the control input of the third switch. 39 37 WITH with I "five :: uh "5 b -eleven §four one ij i §five  " || " eleven 5, S s  one "about : at one 3 I h " "five I. four- § " IEl I l " SI-, 55 W s I I ga 1g