SU1707666A1 - Phased beam receiving array - Google Patents

Abstract

The invention relates to sonar and can be used in hydroacoustic stations to form a fan of the rays of an N-element phased antenna array. The purpose of the invention is to increase the bandwidth of the processed signals and the simultaneous formation of a fan of rays in a given sector of angles. The device contains N transducers 1. The first 8.1 and second 8.2 quadrature beam forming channels, each of which contains a memory block 13 and an accumulating adder 15, serially connected multiplexer 9, a sampling device 10 and an enal-digital converter 11. The goal is achieved by introducing device N complex demodulators 2, block 5 control of pipeline processing of information. a generator of 6 clock pulses and a phase multiplier 7, and in each of the quadrature beam forming channels 8 a buffer memory 12, a block 14 of the permanent memory and a buffer register 16. 4 Il. 00 C

Description

vj

about

h |

ABOUT

oh oh

2c IK 2Tije $ in. ftjt

The invention relates to sonar and can be used in sonar stations to form a fan of the N-element phased array antenna (PAR) beam. For a flat receiving HEADLIGHT, a fan of beams can be formed either in the angle plane (side-scan sonars) or in the azimuth plane (panoramic sonars).

The purpose of the invention is to increase the bandwidth of the processed signals and the simultaneous formation of twist rays in a given sector of angles.

FIG. Figure 1 shows the structural electrical circuit of the proposed reception headlight; in fig. 2 - the location of the linear array antenna transducers and the directivity characteristics of simultaneously formed beams; in fig. 3 and 4 are time diagrams of processes in different points of reception PAR.

Receiving HEADLIGHTS contains (Fig. 1) N converters 1, N complex demodulators 2, the control inputs of which are connected to the inputs 3 and 4 of the first and second reference signals, respectively, the conveyor processing control block 5, the clock pulse generator 6, the phase multiplier 7 , the first 8i and the second 8: quadrature light-shaping channels, each of which contains a multiplexer 9, a sampling device 10, an analog-digital converter 11, a buffer storage device (memory) 12, a memory block 13, a block 14 of the permanent memory oystva, summytor accumulator 15 and buffer register 16.

Reception PHAR works as follows.

Consider a flat, rectangular receiving HEADLIGHT, in which all the elements in columns (or rows) are joined together. This case corresponds to the reduction of a rectangular LAMP to a linear one, in which the beam can scan only in one of two coordinates: the azimuth or elevation. The plane wave (Fig. 2) falls on a linear array of N transducers, which are uniformly distributed along the x axis with an interval d (usually half the wavelength, i.e. A / 2). Let a be the angle of incidence of the wave, then the signal received by the 1st converter will be a time-delayed copy of the signal s (t) received by the (1 + 1) th converter (assuming no other signals and noises) by

At | sina 7ЈSina

sin a Wl

0)

where c is the speed of sound in water;

fo is the center frequency of the received signal spectrum.

To receive a signal arriving at an angle a (in acoustics the term antenna compensation in the d direction is accepted), it is necessary to form the sum

dt, t) -i |: 5 t-ii-0bt - s t- (i-oj ";" it ..

(2)

In sonar, the initial phase of incoming signals is always random. In this case, digital shaping of the directivity characteristics (fan beams) in order to reduce the amount of equipment used is advisable to be performed at zero frequency using the in-phase (cosine) and quadrature (sine) components of the received signals. To obtain the algorithm of the proposed reception PARAM, we move from the real s (t) to the analytical Z (t) signal and select its complex envelope s (t) Z - (t) A (t) exp (J ojb t), then

s (t-k At) (i-k At) A (t-k At) sho (t-kA t). The complex k-ro converter envelope has the form

Ak ((t-kA OexpUtUok At). (3) Substituting formula (3) and expression (2) f, we obtain

, Mbt, (4)

where Y (a, t) is the complex envelope of the signal at the output of the receiving HEADLAMP compensated in the direction a.

Using the Euler formula, we write the product of complex functions in expression (4) in algebraic form

45 lit-Utle.p (-iatk & tl.Atll-kbtVi 5U-l) {cob J01 it - j, nCJ0 and bl) Ac (I -1 ft.), Ul + - "SU-1 & Us .nco.Ul j Ab (t V ЫЧ "Ц t-Mt-kbl .v" ockbi. (5) 50

Substituted expression (5) into formula (4) and assumed that kub At.

VU.D JrZfAeH-O-iU coslp,., 55: n

 Ml-And Hb nlf,, 1 rrS Aslt-ИЫ)

J N,

  COStf,., - Ac ({.- (i-i} bt);.,

- (D) M.KD). (6)

Algorithm (6) describes the work of the reception PARAMON, compensated in the direction a. To obtain a fan of rays symmetrically located in the sector of angles Gfc relative to direction a (Fig. 2, the central beam is shaded), instead of the coefficients cos and sin / c-1 in the algorithm (5, other coefficients should be used

/

. 5; n (, “N,., (“) - 6ip (() j) | t / n, 2, ...- p

MtN,

CD where M is the number of side rays formed;

m is the number of the side beam (positive in the right half-vector and negative in the left), measured from the central beam.

The signals from the outputs of the transducers 1 of the receiver PARA come to the complex demodulators 2. At the outputs of which the in-phase and per-component components of the signals of each of the transducers are separated. To the control inputs of the complex modules; Lhtor from the terminals 3 and 4 receive the reference voltage with a frequency equal to the center frequency of the spectrum of the received signals, and are out of phase relative to each other by 90. The in-phase (cosine) components from the first outputs of complex demodulators 2 are fed to the N inputs of the analog multiplexer 9i. and the quadrature (sinus) components from the second outputs of the complex demodulators of the 2 – nd N input to the analogue multiplexer §2- Next, the processing in the quadrature channels is performed identically. Consider the cosine / ram channel.

The operation of the receive PARA is illustrated by the timing diagrams shown in FIG. 3 and 4, in which M-N-4 is taken to simplify the figures, and the digital signals represented by the codes are conventionally shown converted to analog form,

FIG. An exemplary view of the signal from the output of the first transceiver of the reception PARAM is shown, FIG. Zb-d - in-phase components of the signals of all four transducers. Multiplexer 9i interrogates the first outputs of N complex demodulators 2 in a time less than the sampling interval To.

Tsg2 / KdR. (8) where F is the bandwidth of the signals used;

Cd 2 - sampling rate. Sequential polling of the outputs of quadrature demodulators leads to the appearance of time delays At between the 5 signals of the quadrature components of adjacent PHAR converters

At -To / (N-1). (9) i.e. the delay of the signals Ac (t-k A t) and As (t-k A t) is realized, where. 1. 2, 3 10 (according to (6)). Further segments of implementations. corresponding to the signals of the transducers 21-24 (Fig. 3a), are fed to the device U of the sample, which is controlled by pulses from the second output of the control unit 5, 5 which also follow with a period At (Fig. 3b). and carry out the sampling of incoming signals and storing sample values (Fig. W).

Analog-to-digital converter 111 0 is triggered by pulses coming from the third output of control unit 5 (FIG. 3), and by the time these pulses are finished completing the conversion of sample values (FIG. 3) to digital codes with a period of A t (according to (9)) are stored in a buffer storage device 12i of capacity N SLSV. The multiplexer 9i and the buffer memory 121 operate synchronously, since they are controlled by a single bus 0 of addresses received from the first output of the control unit 5 (Fig. Зк). The read / write input to the buffer memory 12i from the fourth output of the control unit 5 receives the write and read signals 5 (Fig. Zl).

In the time interval (to. 14) (Fig. Zl), the wasp, silt & c-blu with the track control signal level, in the time interval (u, To) the control signal raven unit 0 and information is read from the buffer memory 12 ). Reading from this memory is performed with a speed of rJ times more than writing, therefore, at the time interval (t4, TO), the eblock codes accumulated on the interface (to, 14), the addresses on this interval, are read. also change N times more often (Fig. 3k). In the time interval (c. To), the memory unit 13i operates in the write mode, the read / read signal is received from the fifth output of the control unit 5 (Fig. 4m, the recording is also zero), the addresses are received via the n bus (n log2N ) the lower bits of the sixth output of the control unit 5 (Fig. 4n). Thus, in the interval (w, To), the sample codes are overwritten from the buffer memory 12i into the memory unit 13i, the capacity of which also comprises the terms. On the interval (That,), the buffer memory 12i is transferred to the recording mode and produces

recording the next group of N codes of the cosine components of the PAR signal converters.

On the interval (To, la), the memory block 13i is transferred to the read mode (Fig. 4m) and at this interval all recorded information (N samples) is read M times (by the number of beams formed). In the described example, beams are formed from samples in In this case, on the address bus, the information is changed MNH6 times (Fig. 4n, the interval (To, te)).

Similar processes take place in the channel for processing the sinus components of the transducers of the receiver PAIR. Thus, at the outputs of blocks 13i (Fig. 4o) and 13 memories, we have cyclically repeated (M times) sequences of sample codes of the quadrature component signals of the HEADLAMPS transducers corresponding to previous sampling intervals (to. To).

In the sonar antenna arrays, the number of converters N is usually small and does not exceed several tens (for horizontal or columns), the width of the spectrum of the signals used does not exceed several kilohertz. In this case, it is advisable to move from parallel execution of the operations of algorithm (6) to sequential, which makes it possible to make maximum use of the high performance of a modern digital element base with a proportional (N number) simplification of the device. The time To / M is given to form the output samples of the quadrature components of one of the beams. During this time, all operations of the algorithm (6) are performed (for one ray). The multiplication and addition operations in square brackets of the algorithm (6) are performed by the phase factor 7. which contains four multipliers, an adder and a subtractor. Cycleically repeating sequences of codes of counts of the cosine (Fig. 4o) and sine components of the PAR transducer signals go to its first and second voles, respectively, and the coefficients of coelectric signals - i (m) (Fig. 4p) and -i ( m) from the outputs of the permanent memory units 14i and 14j, which are controlled by the address bus received from the sixth control unit 5 (FIG. 4H). The weights are given in this order: the N coefficients of the first ray, then the N coefficients of the second ray, and so on. In our example, the cosine coefficients of the first ray are arbitrarily chosen as follows: 1, -2.

2, -1. the second beam: 2, 1. -1, -2; third ray: -1, 2, 1, -2: fourth ray: 1, -2. -2 1 (Fig. 4p), on the (M + 1) th cycle, zeros are output (interval (t4, To), Fig. 4p).

FIG. 4p shows a partial product of Ac (l-1) cos wee | - 1. calculated for sampling the signals (Fig. 3) and the selected values of the coefficients of all four rays. FIG. 4c shows a process diagram for the cosine output of the phase multiplier 7, FIG. 4t is at the sinus output of the phase multiplier 7. the corresponding expressions in square brackets of the algorithm (6), calculated sequentially for

all four rays (in our example) using weights determined by formulas (7).

The process sample codes from the outputs of the phase multiplier 7 are fed to the input of accumulating adders 15i of the cosine channel and 15 sine channel, which implement the operation of summing the algorithm (6). The addition of each new count with the amount already stored is synchronized.

impulses coming from the eighth output of the control unit 5 (fig 4u) to the input Record accumulating adder. After adding N consecutively received samples, the contents of the accumulating

adders 15 (figs. 4f, x) are rewritten into buffer registers 16) figs. 4h, yr) pulses input to the Record of the buffer registers 16c of the seventh output of control unit 5 (Fig. 4c), and then the overflow adders 15 are reset to zero reset pulses (Fig. 3b) input to Reset from the second output of control unit 5 .

Thus, in accordance with algorithm (b), the quadrature components of the first ray response (time interval (ts. Te). Fig. 4h, u) are formed at the outputs of the buffer registers 16 with an accuracy of up to a constant multiplier 1 / N. then second

(interval (te. t)), third (interval (p. te)) and fourth (interval (ts, 2To)). Consistent in time the issuance of signals of different rays is very convenient when using, for example, television

monitors for displaying sonar information. In this case, the output signals of the fan of the rays are displayed along the line, and a pause in the output signals (interval (To. Ts). Fig. 4yu) can

used to reverse the electron beam of the monitor indicator.

It is known that if the antenna array beam is formed by introducing time delays into the transducer signals, it is fundamentally absent for the signal bandwidth. If a beam of a known lattice is formed by using fuzzers, the bandwidth (in percent) is approximately equal to the beam width (in degrees). In the proposed receiving PAR, a combined method of shaping the fan of the rays in a given sector of angles is used: the antenna array in the direction of the bisector of a given sector is compensated by introducing time delays that make up the signal from the transducers due to the serial time multiplexers, then the fan of the beams relative to the compensation direction ( sector bisectors) is formed by the phase method. In the worst situation, when the sector of surveys is equal to the double compensation angle, counted relative to the norms for the HEADLIGHTS. the angle of the greatest deviation of the beam in the proposed device is two times smaller than the maximum ulz of the beam deviation (when viewing the same sector) in devices with phase shafts, which makes it possible to double the bandwidth of signals processed by the HEADLIGHTS,

With the help of a preemptive receiving HEADLIGHT, a fan of rays lying in the cross: a torus on the left with the norms can be formed (figure 2). The iQ of the multiplexer 9 changes and the magnitude of the coefficients stored in blocks 14 of the persistent storage device, and at a rate of Pc ,. u -:: i.iemstsv by. Lyme P) the sign in front of the angle a is reversed. L / - and fans of the left and right sectors can be exported in time successively during the sampling interval To.

Claims (1)

Claims of the Invention A Phased Receiver Antenna a ccv.ep- Oi a. The gm transducers, the first and second redirect beam forming channels, each of which contains a memory block and an accumulator sum, a serially-connected multiplexer, a sampling device, and an analog-to-digital converter, such that. In order to increase the bandwidth of the processed signals and simultaneously form a fan of rays in a given sector of angles, N complex demodulators were introduced; ::; fu a clock pulse generator and a one-time multiplier, and in each of the quadrature channels of the beamformer - a buffer apo-5 device, a block of permanent memory and a buffer register, with the output of each of the N converters connected to the input of the corresponding complex demodule 10 of the torus, the first output which is connected to the corresponding input of the multiplexer of the first quadrature channel, the second output - with the corresponding input of the multiplexer of the second quadrature channel. 15, the first and second control inputs of the complex demodulators are respectively the inputs of the first and second reference signals, the output of the analog-digital converter is connected via a buffer memory to a memory unit, the output of which is connected to the corresponding input of the phase multiplier, the first and second the outputs of which are connected to the input of the corresponding accumulator 5 of the adder, the output of which is connected to the input of the buffer register, the output of which is the output of the corresponding quadrature channel, the first control unit of pipeline information processing is connected to the address inputs of multiplexers and buffer memories, the second output is connected to the control input of the samplers and 8 ABOUT - SUBOSS AND m: -. D-ft S. Mmtsts15 ditch, third output - with an input Starting analog-digital converters, the fourth output - with Write, read buffer memory devices. the fifth output - with the input Record / write of memory blocks, and the sixth output is combined with the addressable ones in the modules of the la - - and CONSTANT BLOCKS.: .1 -GT, Poistr. Rhi - with. / h: .. - - t.1 7 g; - gs-- with the third and black Ex; -dg; mi 5 phase multiplier pg. and i-gm .- .. e E-.E-cycles of the memory blocks are the inputs of g and lower bits (n iC 3: K.: l, gc.,. from the conveyor processing control unit, the seventh output of which The input is connected to the input of the Recording buffer registers, and the eighth output from the recording of the accumulating adders, the input of the control block of the conveyor processing of information is connected to the output of the generator. 5 clock pulses. ---- /, / ---- t - r / / -1 .civ -, - / toftf H --ш