SU1451681A1 - Adder - Google Patents

Abstract

The invention relates to the field of computing and can be used in high-performance devices for processing a plurality of numbers. The aim of the invention is to reduce hardware costs. The device implements a sequential-by-bit and parallel-by-number addition algorithm by counting the code of the number of units in bit sections of the terms and then summing these codes with a shift. Compared with the device-prototype, where the increase in the number of summed numbers requires the introduction of new nodes, in this device only the size of the existing nodes increases. The goal is achieved by introducing into the device two combinational adders, a cumulative register and a shift register, as well as new connections. 2 ill., 1 tab. lO (L

Description

The invention relates to computing and can be used in high-performance devices for processing a plurality of numbers.

The purpose of the invention is to reduce hardware costs.

FIG. Figure 1 shows the block diagram of the totalizer for the case of the summation of twelve numbers in Fig.2, the timing diagrams for the delivery of synchronization pulses.

The totalizer contains input registers 1, blocks 2 and 3 of converting the code of a number into a binary code of the number of units, result register 4, intermediate shift registers 5, block 6 of converting a code of a number into a binary code of a number of units, combinational adder 7, shift register 8, combinational adder 9, cumulative register 10, as well as synchronization inputs 11 and 12 and reset input 13.

The device works as follows.

The terms are placed in the input registers 1. The registers 8 and 10 are reset. At the same time, the input of the blocks 2 is given to the younger bits of the terms. -Blocks 2 form at their outputs the sum of the bits fed to their inputs. The lower bits of these sums are supplied to block 3 along with the bit from the output of register 10.

At the low-bit output of block 3, the low-order bit of the sum of all input numbers is formed. The transfer bits from the outputs of the high bits of blocks 2 and 3 are written into intermediate registers 5 over the pulse section at input 1

The number of outputs q blocks 2,3 and 6 can be determined by the formula

q tlog Kj + 1,

where K is the number of inputs of block 2 (3,6).

one

Consequently, the number of bits of the intermediate registers 5 shift

n tlogiK,

where log, jK is the whole part of the number log

The input of block 6 is supplied with bits from the outputs of registers 5. On. the output is the sum of the carry bits, which is fed to one input of the combinational adder 7. The number

0 5

ABOUT

0

five

five

the inputs of the combinational adder 7 is equal to the number of outputs q of block 6.

The pulse at the input 12 is written to the register 8 and shifted to the right in intermediate registers 5. The pulse from the pulse at the input 12 is shifted to the right in the register 8. The freed bit is filled with zero. At the output of block 6, the sum of the next carry bits is formed, which over the following edge of the pulse at input 12 is summed up in register 8 with the corresponding bits of the sum of transfers. After the front of the nth pulse at input 12 in register 8, the sum of the carries of a given bit slice of the input binary numbers is formed.

Register width 8

S q + n,

where q is the number of outputs of the block 6n is the size of the registers 5. Then, along the pulse front at the input 11, the following occurs:

1. shift to the right in input registers 1, while the next bit slice of input numbers is supplied to the inputs of blocks 2;

2. shift to the right in the register 4 of the result, while the next bit of the sum of the input numbers is entered into the input register;

3 .. summation in the cumulative register 10.

The cumulative register 10 is connected to the input of the combinational adder 9 with a right shift by one bit, which allows the use of the register 10 without the shift register. The bit of the combinational adder 9 is equal to the bit S of the register 8. The bit of the register 10 is equal to S + 1.

The pulse at input 11 is written to intermediate registers 5. With the arrival of a pulse, register 8 is zeroed out. Next, after the next n pulses at input 12, register 8 will be transferred to the higher bits of the next bit slice of input numbers at the input of register 4 is the next bit of the sum of the input numbers.

With the arrival of the next impulse on. input 11 in register 10 will carry the transfer to the most significant bits of the sum of the input numbers, and register 4 will not contain the next bit of the sum.

After the front of the m-ro pulse at input 1 1, register 4 will contain the sum of the input numbers.

Thus, t + 1 pulses must be fed to input 11, where m is the size of the terms .svHa input 12 must be fed by n pulses between every two pulses at input 11. To input 13 it is necessary to feed m pulses after each cut of the pulse at input 11 .

Primer p. It is necessary to add 12 three-bit binary numbers.

The terms are loaded into registers 1 in accordance with the table.

The slice of the zero pulse at input 11 is written to the registers 5: Register number Code

5.100

5.201

5.301

5.4 01

At the input of block 6, code 0111 appears, at its output - code 011.

On the front of the first pulse at input 12, summation occurs in register 8. Code 00110 will be rem. Rem also registers 5. A code 0000 appears at the input of block 6, code 000 appears at the output.

Over the first impulse section at input 12, information in register 8 is shifted. It will contain code 00011. On the front of the second pulse at input 12, register 8 is summed.

It will contain code 00011.

On the front of the first pulse at input 11, the following occurs:

1. shift to the right in register 4, it will be 1 x x x x x, where x is an undefined character;

2. summation in register 10, it will be code 000011;

3. shift in registers 1.

At the inputs and, accordingly, at the outputs of blocks 2:

Block number

Register number

5.1

5.2

5.3

5.4

At the input of block 6 output - code 011.

ten

15

25

thirty

35

Code

01 01 01 00 - code 1110, on

After the third pulse at input 12, a write occurs and a shift in register 8. It will contain code 00011.

At the input of block 6 there will be a code 0000, at the output - a code 000. On the front of the fourth pulse at input 12 in register b there is a summation, it will contain 00011, which is fed to the first input of adder 9, the second input is given code 00001. At its output - 20 code 000100.

On the front of the second pulse at the input 11 occurs:

 1. shift information in the register 4, it will be 01 x x x x;

2. Record in the register 10 of the code 000100;

3. shift in registers 1.

At the inputs and outputs of blocks 2: Block number Code at the input

2.11001

2.21010

2.31100 On

Exit code

010

010

010

40

the input of register 4 will be code 0000, the output code 000.

Continuing in this way, after the seventh pulse at input 11, we obtain in register 4 of the result the sum of the input terms, i.e. 0101001.

Claims (5)

 1. shift information in the register 4, it will be 01 x x x x; 2. Record in the register 10 of the code 000100; 3. shift in registers 1. At the inputs and outputs of blocks 2: Block number Code at the input 2.11001 2.21010 2.31100 On Exit code 010 010 010 the input of register 4 will be code 0000, the output code 000. Continuing in this way, after the seventh pulse at input 11, we obtain in register 4 of the result the sum of the input terms, i.e. 0101001. 40 Invention Formula ha, the outputs of the lower bits of the transient shift registers are connected to the corresponding inputs of the first additional block for converting the number code to the binary code of the number of ones, the outputs of the higher bits of the second additional block for converting the code of the number to the binary code of the number of ones are connected Q to the inputs (1 +1) -th intermediate shift register, and the output of the younger ra: zrd is connected to the input of the lower digit of the result register, the input of the shift of the input registers, the result register, 5 code of the number of units, the remaining inputs that and the inputs of the intermediate records are connected to the codes converting the code of the number into a binary code of the number of units, the output of the shift register, the output of the first combinational adder is connected to the input of the shift register, all bits of the output of the shift register are connected to the first input of the second Raman adder, the second input of which is connected to the output of the higher bits of the cumulative register, the youngest the bit of which is connected to the first input of the second additional block for converting a code to a number in binary the shift histories are connected to the first synchronization input of the device, which is characterized by the fact that, in order to reduce hardware costs, the device contains two combinational adders, a storage register and a shift register, and the output of the first additional block for converting the number code to the binary code of the number of ones is connected to the first input of the first combinational adder, the second input of which is connected to the bits. with the n-th to (q + n-1) -and, where 20 the lower bit of the number code to binary number conversion code block, the write input of the cumulative register is connected to the first synchronization input of the device, the write and shift control input of the shift register and the shift input of the intermediate shift registers are connected to the second synchronization input of the device, output the low-order (1 + 1) -th intermediate shift register is connected to the (-1 + 1) -th input of the first conversion unit of the number code to the binary quantity code n is the length of intermediate registers; the reset input of the shift shift register; q - the number of bits you connected to the device reset input, the course of the first additional block code of the number of units, the remaining inputs of which are connected to the codes converting the code of the number into a binary code of the number of units, the output of the shift register, the output of the first combinational adder is connected to the input of the shift register, all bits of the output of the shift register are connected to the first input of the second Raman adder, the second input of which is connected to the output of the higher bits of the cumulative register, the youngest the bit of which is connected to the first input of the second additional block for converting a code to a number in binary code of the number of units, the remaining inputs of which are connected to the codes low bit block conversion-. neither the number code in the binary code of the number of units, the write input of the cumulative register is connected to the first synchronization input of the device, the write control and the shift register shift input and the shift input of the intermediate shift registers are connected to the second synchronization input of the device, the low-order output (1 + 1 a) th intermediate shift register is connected to the (-1 + 1) th input of the first block of converting a number code to a binary number code h; :; : 5gt5; g; Well "SJ v: 4h hG 0 2.1 get angry cdSuz tS Cusur ng 660 7 / P 7J bv rc "about : : s: to X Sij x yr 2.3 five pg 5.Z Sh 5.3 five P s. htgg Lighted up I i M I I 7O 1 I I M figure 1