SU1446630A2 - Scanning converter - Google Patents

Abstract

The invention relates to amplifying devices 4 with pulse-width signal conversion and can be used in analog computers. The aim of the invention is to improve noise immunity. The multiband scanning converter contains the first and second adders 1 and 2, integrator 3, relay blocks 4 ,, ..., 4, generator of 5 adjustable IT-pulses of adjustable frequency, Johnson's counter 6, block 7 of the function Logical threshold, input 8 and output 9 The multi-zone deploying converter operates in a self-oscillating mode, the relay blocks are periodically put into operation, in case of interference, the frequency of the variable-frequency clock generator signal changes abruptly, which leads to faster connection Relay Blocks and Eliminate the Effects of Interference. 8 il. (L

Description

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The invention relates to amplifying devices with a pulse-width conversion signal, can be used in analog computers and is an improvement of the basic invention according to the authors. St. No. 1332336.

The purpose of the invention is to improve the noise immunity .1Q

Figure 1 shows the functional diagram of a multi-band deploying converter} in figure 2 - functional. nA ring circuit diagram; FIG. 3 is a functional block diagram of the function Logical Threshold; figure 4 is a functional diagram of the generator and the output pulses adjustable frequency; FIG. 3 is a functional diagram of the Relay1 of the Shoig block; FIGS. 6-8 are 20 waveform diagrams.

The converter contains the first and second adders 1 and 2, the integrator 3, relay blocks A ,, ..., 4j ,, generator 5 clock pulses, counter 6 John-25 son, block 7 of the function Logical threshold, input 8, output 9, V triggers 10 ,, ..., 10 ", element OR-NOT 11., counting input 12, bit outputs 13 ,,., ..., 13, elements AND 14 ,, ..., | 4g, ele - 30 ment OR 15, the inputs of the function block Logical threshold 16,, ..., 164 ,, output 17, high-speed generator 18 HNmynbCOB, frequency divider 19, NO 20 element, BAN 35 21 and 22 elements, OR element 23, the manager. input 24, output 25, first, second, third, fourth, fifth, sixth and seventh scaling resistors 26-32, key transistor 33, operational 40 amplifier 34, information input 35, threshold adjustment input 36, output 37, input 38 displacement, zero potential bus 39.

In Fig.6, 7 and 8 are indicated: x (t) -45 signal from input 8; Y (j (t) is the output signal of the integrator 3; Yp, - (t), Yp2 (t), Ypa (t) is the output signals of the relay blocks 4 ,, .. ,, ,, 4 ,; Ya, (t) is the signal to output 9; Q ,, Qg, RZ signals ng outputs of counter 6 ;, f is the frequency of the generator 18 pulses of high frequency; k is the frequency division factor; + A is the maximum amplitude of the pulses at output 9; modulation zone; t is the moment of time reorientation of the relay block.) / SU / / Bpf - free level

threshold values Jt B; tj, is the initial moment of time when Log is present on the first output of counter 6. one.

Multi-zone scan converter operates as follows.

The ring counter 6 (FIG. 2) contains D-flip-flops IO, ..., 10 "connected in series, the C-inputs of which are connected and form the counting input 12 of the codes of the D-flip-flops 10, ..., 10 are connected to the inputs of the element IL-NOT 11, the output of which is connected to the input of the D-trigger 10, the low-order bit, and the output of the higher-order bit 13, the ring counter 6.

The function block of the Logical threshold (FIG. 3) contains the elements AND 14 ,, ..., 14 and the element OR 15. In FIG. 3, the block is made with a dp of operation with a ring counter 6 for 5 bits.

The oscillator 5 clock pulses adjustable frequency (figure 4) contains the generator 18 pulses of high frequency, the frequency divider 19, the element NOT 20, the elements of the function BAN 21 and 22, the element OR 23.

The relay unit (FIG. 3) contains an operational amplifier 34, a key transistor 33, large-scale resistors 26-32.

The first and second adders 1 and 2 have a single transfer coefficient. The output signal of the integrator 3 controls the relay blocks 4, ..., 4c, which are made with a non-inverting hysteresis loop and symmetrical switching thresholds ± V. The output of these blocks varies discretely within ± A / n. Availability Log. 1 at the switching threshold adjustment input leads to a reduction in the threshold levels.

Availability Log. On the control input 24 of the generator 3 clock pulses of adjustable frequency ensures the minimum frequency of the output pulses. When submitting the log. 1, the frequency rises to the maximum value.

The ELOC function Logical threshold 7 forms the output of the log. 1 if there are one or more redundant code I at the outputs of the counter 6. The allowed combination of the counter 6 is a combination with one 1. In this

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In the case of a signal at the output of block 7 of the function Logical-1, the threshold is equal to Log. ABOUT.

When considering the work, we restrict n 3. Let us also assume that the switching thresholds of the relay blocks 4 1 satisfy the condition | B, 1, |, and 1c ,. The presence of 1 at the input of the threshold adjustment of the corresponding burdock block A leads to the fulfillment of the conditions

| in; | | Bo1.

When switching on, relay blocks A ,,,,. ,, ..4, Aj are set to arbitrary, for example positive (Figs. 66, c, d) states. The output signal of the integrator 3 increases in the negative direction of the Yuma direction (Fig. 6a), which leads to

15 is a relay block 4 ,. With the arrival of the next clock pulse from the generator output 5 clock pulses of adjustable frequency (FIG. 1), the condition (FIG. 8a) is fulfilled (1

sequential switching of relay blocks 4,, Aj, (6 b, c). Output-20 Is, - | B, |. The signal signals of the relay blocks 4, 4 h are mutually compensated (Fig. 6, c, d). This entails the transition of the relay, and the relay block 4, passes into the mode block 4 in a static state - periodic self-oscillations (Fig. bb), and the occurrence of the autocool mode providing at the output 9 a stream of impulses in the path of the relay block 4

owls with a zero value for the period of self-oscillations (fig.bd). The output signal of the integrator 3 is in the form of a symmetrical saw with an amplitude normalized by the switching thresholds of the relay unit 4 (fig.b).

The presence of the signal at the input 8 (fig.ba) leads to a change in the derivative of the sweep on the code of the integrator 3 and entails a change in the duty cycle of the pulses at the output of the relay unit 4 | and exit 9 (6 b, d). When condition Ix (t) is satisfied (| A / 3 (the output signal is generated in the first

(Fig.8 b, c). The third clock pulse provides Q 1- (Fig. 8g) and the condition (1c, 1 lBj) c | B, l

(Fig.8a), which leads to the static 30 mode of the relay blocks 4, 4 (Fig.8 b, c) and the dynamic mode of the relay block 4h (Fig.8a, d). Thus, the relay is carried out

the operation mode of the relay blocks 4,

4.J, which improves reliability of operation due to a more uniform distribution of power loss between all relay units.

With the appearance of the counter output

the modulation zone bounded by the pre-6 excess 1, the aldemi ± A / 3 fails. Starting from the time of the work, as the free t

.J when Ix (t) | | A / 3 | (figla), the relay unit 42 is reoriented into a positive state (fig.7 b, d) and transitions to the second module area (fig.7e).

SU level may be occupied at once by two or more threshold values of relay blocks 4 ;, ..., 4.

As soon as the output of counter 6 appears extra, the 5-clock pulse generator is switched to high-frequency generation mode and the counter 6 is reset. The duration of this process is 10-10 times higher than the natural frequency of self-oscillations, therefore the system returns to the allowed state is achieved almost instantly without any significant violations of the operation algorithm. After the liquidation of the excess 1 generator frequency, 5 clock pulses are set to the nominal frequency.

The output signals of the relay blocks 4., 4 are summed up (Fig. 7 g, d), which ensures a stable mode of self-oscillations in the second modulation zone.

However, the process of restoring the allowed code occurs at a generator frequency of 5 clock pulses and may be unacceptably large in time, which leads to a violation of the algorithm of operation. To eliminate this drawback, a block, 7 Lo functions, is entered.

gnarish threshold. If at the outputs of the ring counter 6 at least one extra 1 at the output of block 7 of the function, the Logical threshold appears with a log. G.

Availability Log. 1 at the control input of the generator 5 clock pulses of adjustable frequency leads to

Q sharp increase in the frequency of its output pulses.

At Q, 1 (Fig. Bd), the condition (1B, | IBJ) | Bjfc (Fig. Ba) is fulfilled and in the switching mode, the relay block 4 is running ,. With the arrival of the next clock pulse from the generator output 5 clock pulses of adjustable frequency (FIG. 1), the condition (FIG. 8a) is fulfilled (1

, - | В, |. This entails the transition of the relay unit 4 to the static state and the occurrence of the autowheel mode in the path of the relay unit 4

, - | В, |. This entails the transition of the relay unit 4 to the static state and the occurrence of the autowheel mode in the path of the relay unit 4

(Fig.8 b, c). The third clock pulse provides Q 1- (Fig. 8g) and the condition (1c, 1 lBj) c | B, l

(Fig.8a), which leads to the static 30 mode of the relay blocks 4, 4 (Fig.8 b, c) and the dynamic mode of the relay block 4h (Fig.8a, d). Thus, the relay is carried out

the operation mode of the relay blocks 4,

4.J, which improves reliability of operation due to a more uniform distribution of power loss between all relay units.

With the appearance of the counter output

 6 of excess 1, the operation algorithm fails, since the free

50

55

SU level may be occupied at once by two or more threshold values of relay blocks 4 ;, ..., 4.

As soon as the output of counter 6 appears extra, the 5-clock pulse generator is switched to high-frequency generation mode and the counter 6 is reset. The duration of this process is 10-10 times higher than the natural frequency of self-oscillations, therefore the system returns to the allowed state is achieved almost instantly without any significant violations of the operation algorithm. After the liquidation of the excess 1 generator frequency, 5 clock pulses are set to the nominal frequency.

Thus, a multi-zone sweep converter has a higher noise immunity.

Claims (1)

Invention Formula Deploying Converter Auth. St. No. 1332336, which differs from the fact that, in order to improve noise immunity, the function block Logical threshold was entered into it, the inputs of which are connected to the discharge outputs of the Johnson counter, except for the last, of the relay element, the output of the Logical Threshold function block is connected to the control input of the clock generator. - { YU, g U9  sh w ha I Jh ) 3l jtf g Dy  fl FIG. g Js 17 .З I 35 tt 8h bt Sutli 17 : § .. / / r in d o - | ее / IS 21 17 G 5 7 t t L : Sf vea but one s i I : W CG „Cs about 0 and i o about 8th o same iSflS.