SU1444792A1 - Arrangement for data exchange between processor and users - Google Patents

Description

The invention relates to the field of computer technology, in particular, to exchange systems, and can be used in the construction of automatic control systems.

The purpose of the invention is to improve the performance of the device by providing simultaneous exchange of information between any number of source and receiver subscribers, including data replication, and the subscriber and processor, as well as reducing hardware costs.

FIG. 1 shows a block diagram of the device, FIGS. 2-12 are functional block diagrams of a communication unit with subscribers, a decryption unit, addresses and commands, an information switching unit, and commands, a receiver connecting switch, a command switch, latch registers . receivers and sources, the node of the elements And, the first and the second synchronizer and block interrupt; Fig, 13 - the format of information from the processor; Fig, 14 is a diagram of the operation of the device.

The device (Fig. 1) contains blocks 1 of communication with subscribers, block 2 with op-emit, block 3 interrupts, block 4 switching. Information and commands, block 5 decrypting the address and commands, block 6, command lution 1, processor .7, bus 8, spreading commands, buses 9 and 10 commands to external and internal subscribers, buses (lines) 11 requests, information buses 12 and 13, bus 14 commands to external subscribers, processor command bus 15, bus 16 for wok, signals bus 17 interrupts.

The communication unit 1 with the subscribers contains (FIG. 2) impulse drivers 18, registers 19 and 20, a decoder 21, a synchronization unit 22 and a group of elements 23,

The address decoding unit 5 and the coman (Fig. 3) comprises a node 24 of command elements AND instruction, a command storage node 25, and a decoder for commands and addresses 26.

Unit 4 switching information and commands (Fig. 4) contains a switch

27connection of receivers, registers

28, the source selection, the switch 29 commands, the node 30 of the elements Hj register 31 fixing the status of receivers and

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a fixation register 32, state, sources, bus (line) 33-44 of the internal connections of the unit.

Switch receiver connection 27 (Fig. 5.) contains a group of elements AND 45, a group of triggers 46, a group of elements OR 47, a group of elements AND 48 - 50, a group of elements HE 51, an element OR 52, a group of elements OR 53, a group of triggers 54, element And 55,

The switchboard 29 commands (Fig, 6) contains a group of elements BL 56, groups of elements-And 57, 58, the element OR 59 and the element NOT 60,

Registers 32 and 31 of fixing the state of sources and receivers (Figs. 7 and 8) contain a group of elements OR 61 a group of triggers 62, a group of elements AND 63, a group of elements OR 64, a group of triggers 65 and a group of elements AND 66.

The node 30 of the elements And contains (Fig. 9) five groups of elements And 67 - 71.

The synchronization node 22 consists of two synchronizers 22.1 and 22.2 (FIGS. 10 and 11) containing tires 72, 73 prohibition, trigger 74, element NOT 75, elements I 76-78, trigger 79, elem.nt 80, trigger 81, the element NOT .82, the elements And 83-85, the trigger 86 and the element And 87.

Nodes 24 and 25 of block 5 (Fig. 3) consist of the elements HE 88, 89, the element And 90, the group of elements And 91, the register 92 and the group of elements And 93, Block 3 interrupts (FIG. 12) contains the element HE 94, element AND 95, group of elements AND 96, register of 97 masks, group of elements NOT 98, group of elements AND 99, element OR 100, group of decoders 101, group of elements 10.2, counter 103, element AND 104, generator 105 pulsesB (GI), trigger 106

In FIG. 1, 2, 11, the information bus 107 of the subscriber, bus 108, and 109 of the source control and receiver exchange control signals are shown.

FIG. 12 shows the elements. AND 110 and 111, the element OR 112. FIG. 2 shows the triggers 113 and 114,

The decoders 101 (FIG. 12) consist of AND 115 elements, HE 116 elements and OR 117 elements.

The device provides for the exchange of information on the following paths: subscriber-source - processor 7; processor 7 — subscriber-receiver or group of subscribers-receivers; subscriber source - subscriber-receiver or group of subscribers-receivers.

All subscribers of the system are assigned numbers from 1 to M, where M is the number of subscribers in the system.

In order to ensure the exchange of information on the first path, the processor 7 generates the following sequence of commands: The source If ... transfers information; Receiver No. ... receive information; Exchange with the processor; The end of the exchange.

In order to ensure the exchange of information on the second path, the processor 7 generates the following sequence of commands: Source No. ... transfer information; Receiver No. ... (receivers ...) receive information; Exchange with the processor; The end of the exchange.

Information is exchanged via the third path in the following modes: according to incoming requests from source subscribers (Fig. 1), processor 7 connects the receiver-subscribers they need according to a predetermined hard scheme (for example, source 1 - receivers 1, 2; source - nick 2 - receiver 5; source 3 - receiver 2, etc.); upon receipt of the application from the source, the processor 7 establishes a connection with it (implements the first information exchange path) and receives the exchange control word, in which the source indicates the number or numbers of the required receiving subscribers. The processor 7 reads information about the status of receivers at a given time (the receiver can be in exchange with another subscriber or be free) and, if the receiver is currently busy, the processor stops working with it. In case of repeated receipts of applications from this source, the processor looks at the states of the receivers required by it and, in the event of their idleness, connects them to this source; the combined method of connecting receivers to sources, i.e. some subscribers switch according to the first exchange mode, and

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part - in accordance with the second mode.

In order to ensure the exchange of information on the third path in accordance with the first mode, the processor, when receiving the application from the source, generates the following sequence of commands: Read the status of the receivers; Read the status of the sources; Source K ... transmit information; Receiver No. ... (receivers ff ...} receive information; Interchange.

In order to ensure the exchange of information on the third path in accordance with the second mode, the processor, when receiving a request from a source, generates the following sequence of commands: Source No. ... transmit information; Receiver No. ... receive information; Exchange with a processor; Source No. ... suspend exchange; Read the status of the receivers; Read the status of the sources; Source No. ... transmit information; Receiver No. ... (receivers No. No. ...) receive information; Interchange

The table lists the groups of elements shown in FIG. 2-12, and it is indicated how the number of elements in each group is determined.

The indication that this command is addressed to -block 5 is a code combination containing zeros in the two lower bits, which leads to the opening of the And .90 element and the appearance of a signal with a level of 1, which provides information from the bus 15 through the elements 91 to the decoder 26. The decoder 26 issues a command to the bus 10 and generates a command enable signal. The bus 10 command and the command release signal on the bus 8 arrive at block 4 (FIG. 4) at the command issuing permission node 30. In node 30, via elements 72 (fig. 9), the command via lines 39, 42, 37 goes to registers 31, 32, and switches 27, respectively. Single signals of the initial setup through elements OR 64 are fed to the inputs of the installation in zero state Trigger 65 (Fig. 3), through the OR elements 61, arrive at the inputs of the installation in the zero state of the flip-flops 62 and set them in the zero state. In the switch 27 (FIG. 5), the initial setup signals

arrive through the elements OR 47 to the inputs of the installation in the zero state of the flip-flops 46 and set them to the zero state.

The provision of exchange information by the first path is carried out as follows.

For service requests from blocks

the discharge of counter 103, the signals are sent to descramblers (polls) 101. The number of pollsors 101 is determined by the number of external subscribers. Signal level 1 output

each of the pollsors 101 within the account cycle can appear only once and only with a certain

1 (Fig. 1) is fed to the inputs of the Q blocks of the code combination on the counter. AT

2 and 3. Each block 1 can set as an example in FIG. 12 image- two applications: for the reception, four interrogators are informed. The signal from the level on line 11 and the filing of issuing it 1 at the output of the first (right information on line 11. Applications on the scheme) will be present; only the inputs of blocks 2 and 3 can mask -15 k in the event that if the combination is on with the instructions of the processor 7. If the counter 103 is set to 0000,

processor 7 is free, i.e. is not occupied at the moment servicing of subscribers, and if there are no applications at the inputs of block 3 requiring immediate service, then block 2 examines the service bills. Upon detection of the first application, its number through block 6 is transmitted to

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at the output of the second with a combination of 0111, at the output of the third - with a combination of 1000, at the output of the fourth (left according to the scheme) - with a combination of 1111.

If counter 103 is equal to the number of external subscribers, its readings are reset by a signal with

the discharge of counter 103, the signals are sent to descramblers (polls) 101. The number of pollsors 101 is determined by the number of external subscribers. Signal level 1 output

at the output of the second with a combination of 0111, at the output of the third - with a combination of 1000, at the output of the fourth (left according to the scheme) - with a combination of 1111.

If counter 103 is equal to the number of external subscribers, its readings are reset by a signal with

processor 7, after service level 25 begins with the output of this application.

The servicing of the application includes two phases: the exchange of information and the processing of information. During the exchange of information on the path, the subscriber-processor (processor-subscriber) viewing the quotes in blocks 2 and 3 is stopped and in block 3 is resumed after the end of the exchange, in block 2 it is resumed after the processing of information in the processor 7 is completed.

Upon completion of the exchange with the source or during the initial installation, the processor 7 sends to the bus 15 an End of Exchange command, which is entered into block 5 (FIG. 3), where it is decrypted by the decoder 26, resulting in the output of the decoder 26 command enable signal. The bus 10 command and the bus 8 resolution signal are input to the AND 111 element (Fig. 12) and set the trigger 106 to one state.

A signal with a level of 1 from the output of the trigger 106 is sent to the input of the element AND 104. At the other input of the element AND 104, impulses of a single level are received from the generator 105 of pulses (GI).

The pulses from the output of the GP 105 through the open element And 104 are sent to the input of the counter 103, From the output of each

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interrogator 101 (in this example, the number of external subscribers is limited to sixteen), and the account starts with the first.

In the process of operation of the device from blocks 1 on tires 11 ,. 11 (Fig. 1) in block 3 (Fig, 12), the elements OR 100 from subscribers receive applications for service (signals GI, GP), and on the bus 15, the processor according to the program can set masks of subscribers, which are entered through register 97 through elements AND 96. Elements HE 94 and AND 95 serve to decipher the address of block 3. The set mask corresponds to one in the corresponding register register 97. From the output of each bit of register 97, signals are output to the inputs of elements HE 98, as a result, at their outputs, a code is formed that is inverse to the code stored MUS on the register 97.

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Thus, in the presence of

the input of one of the elements AND 99 simultaneously of the signal of a single level from the corresponding element of HE 98 (the sign of the absence of a mask), the signal from the subscriber and the interrogation signal from the interrogator 101th output of the corresponding element of AND 99 appears a signal with a level of 1, which is interpreted as an auto-break signal and.

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through the element OR 100 via bus 17 enters into. processor 7.

At the same time, from the bus 17, the auto-rupture signal through the OR element 112 112 resets the trigger 106, which prevents the generation of pulses from the generator 105 to the counter 103.

In addition, the auto-break signal provides the passage of information from the counter 103 through the elements 102 to block 6. The information from the counter 103 is the number of the subscriber requiring the service. Upon receipt of the auto-break signal, the processor 7 terminates the execution of the program and serves the download, the number of which enters through block 6 from block 3. After the auto-break program is executed, the processor 7 resumes the execution of the interrupted program. In this way, the exchange of subscriber requests is initiated.

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From register 28 (FIG. 4), bus 3j is sent to switch 29, the command is sent to the selected source, which passes through AND 57 elements (FIG. 6) and OR 56 passes to AND 58 and allows the command to pass. Switching is done in the same way.

When receiving a call from a source subscriber, processor 7 generates a command to Source No. ... to transfer information. The command contains the command code and subscriber number. Subscriber number Q command bus with the selected source. In the Komavda, the position is indicated.

The command from the processor via bus 15 (Fig. 3) goes to block 5 at the input of node 24, with two lower bits being given to the inputs of the HE elements 88, 89, the rest (command code and external subscriber number) to the inputs of the AND elements 91. The indication that this command is addressed to block 5 is a code combination containing zeros in the two lower bits, which leads to opening of the AND 90 element and the appearance at its output of a signal with the level jj providing the bits of the code combination from bus 15 through elements AND 9T per node

25 and the decoder 26.

At node 25, the high bits of the code combination (processor instruction code) are assigned to register 92 and if there is a enable signal from the decoder

26 through the elements and 93 fall on ia 9.

The source number is fed to the input of the decoder 26, where the command permission signals are outputted. The command arrives on the bus 10 and is brought to block 4 (Fig. 1), block 3, block 2. By this command in

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In blocks 2 and 3, the wok queuing is stopped.

In block 3 (Fig. 1), the command on bus 10, accompanied by the enable signal on bus 8, is input to: AND 111 (Fig. 12), with the result that trigger 106 is set to zero and pulses from GI 105 through the element 104 at the counter 103 is not received.

In block 4, through node 30 (FIG. 4), via bus 36, the command code is fed to source selection register 28, where the corresponding register bit 28 is set to one.

The command via bus 9 enters unit 4 to switch 29, where commands through elements OR 59 via bus 14 enters unit 1 of the selected source.

From register 28 (FIG. 4), bus 3j is sent to switch 29, the command is sent to the selected source, which passes through AND 57 elements (FIG. 6) and OR 56 passes to AND 58 and allows the command to pass. Switching is done in the same way.

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- Q command bus with selected source.

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In addition, a signal arriving on the bus 33 sets one of the flip-flops 65 to the single state (Fig. 8).

The command in block 1 (Fig. 2) enters the bus 14 to the decoder 21. The decoder 21 generates an information transmission permission signal, c which from the output of the decoder 21 enters the input of the trigger 113 and sets it to a single state, which allows for information from the register 19 through the elements 23 to the bus 12. From the output of the decoder 21 via line 72, a signal prohibits the subscriber’s application from passing through node 22 via line 11 to blocks 2 and 3. At the same time, the trigger 74 of node 22 (Fig. 10) is set to one, with the result that At the output of the NOT 75 element, there is a signal with a level O, coming at the input of the element And 76, and an application (GI signal) from the bus 108 through the element 76 and & Bus 11 does not arrive. In this case, the application via element 77 is available to the subscriber-receiver unit 1.

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Then processor 7 issues a command to Receiver No. ... to receive information (in this case, the command specifies the processor number), the command goes to block 5, in which the command and subscriber number are allocated, the command and subscriber number are received at the inputs of node 25 and decoder 26 (Fig. 3). The decoder 26 picks up the command to internal subscribers and puts it on bus 10 and the command enable signals. Commands on buses 9 and 10 and the command enable signal on bus 8 arrive in block 4 In block 4, the command to external subscribers goes to switch 29 (Fig. 4), and the team to internal subscribers goes to node 30. At node 30 (Fig. 9 a) allowing the command to pass through to the elements 70 and permit the passage of the command from bus 10 to bus 38. The command on bus 38 arrives at register 31 and switches 27, 29 (Fig. 4). In register 3-1, the command sets the corresponding trigger 62 of the selected receiver to one.

The team on bus 38 is available to everyone. switches 27, but arrives only on the one whose source is selected in the previous command (the number of switches 27 in the scheme is determined by the number of sources and additionally the processing node). In the switch 27 (Fig. 5), the signals through the AND elements 45 are fed to the inputs of the flip-flops 46, and the corresponding trigger of the selected receiver is set to one.

In switch 29 (Fig. 6), the receiver selection command via bus 38 enters the inputs of the OR 56 elements and allows the team to the external subscriber from bus 9 through the corresponding AND 58 elements to one of the 14 buses. If there is a command code on the bus 38 by the OR elements 59, HE 60 prohibits the issuance of information from register 28 (FIG. 4) via bus 33 through AND 57 and SHSh 56 (Fig. 60 to the corresponding AND 58 and therefore prohibiting the switch 29 and the device as a whole from false messaging). .

A bus 14 command is issued to block 1 (Fig. 2) of the selected receiver to the input of the decoder 21. As a result,

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In order to decode the command at the outputs of the decoder 21, signals are generated that set the trigger 114 to one state, allow reception of information from the bus 13 to the register 20, prohibit the issuance of the application by the receiving subscriber to line 11, the latter through line 73 is output to node 22 (FIG. 11), to the input of the trigger 81 and sets it to one state. A single signal from trigger 81, inverted by the element NOT 82, is output to the input of element 5 and 83 and prohibits the issuance of the application (sig nal) from the bus 109 through the element 83 to the line 11. At the same time, the application via bus 13 is available to the subscriber - to the source, since at the other input of the And 84 element there is a signal with a level 1 from the output of the flip-flop 81. Then the processor 7 generates the command Exchange with the processor. The team enters block 5.

In block 5 (FIG. 3), node 24 allocates a command and expands it onto node 25 and decoder 26. As a result of deciphering the command Exchange with the processor, the command from the register 92 is blocked on the bus 9 and transmitted to the line 8. Command on line 8 is available to all blocks 1, but is only communicated to block 1, which received the processor command Source # ... to transfer information

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ation.

as a result of executing the command Source No. ... transmit-information from register 28 (Fig. 4) via one of the bus lines 33 to the corresponding switch 27, a potential signal with a level 1 is output to the inputs of the AND elements 45 (Fig. 5) When executing the command to the Receiver No. ... to receive information on the inputs of the switches 27 from node 30, a code is determined, which determines the selected receiver, which goes to the first inputs of the And 45 elements of each switch 27 via bus 38.

As a result of executing these commands in the switch 27 selected by the first command (FIG. 5), a trigger selected by the second command will be installed in the trigger group 46. The unit level signal from the output of the selected trigger 46 is passed to the inputs of the corresponding 1x elements 48, 49 than switching of the information signal lines 12 and 13 of the source and receiver, respectively, is provided.

The signal from the source as well as other information exchange control signals produced by the source from the output of block 1 via the signal lines of the information signal bus 12 are entered into block 4 at the input of the selected switch 27 and fed to the inputs of the corresponding And 48 elements. And elements 48 , on the first inputs of which there is a signal with the level 1 from the output of the trigger 46, provide the exchange control signals from the information signal bus 12 along the signal lines of the information signal bus 13 to the input of block 1 (Fig. 1), where the signal is G vzdaets at node 22 (FIG. 11) to the input of AND gate 85, an open signal level 1 from the output of flip-flop 81.

The command Omen with a processor, receiving another information step from block 5 via line 8 to the block.

the input of the receiver unit 1, entered into the signal UN from the receiver from the bus node 22 to the input element I 87, opened 109 (Fig. 1) passes through that level 1 signal from the EXIT node 22 (Fig. 11) of the trigger receiving unit 1 81, as a result of which the signal appears on the information sig

the scrap from the output of the element 87 and the trigger 86 is set to one; the signal from its output enters the input element And 85, which provides the signal GI from the information signal bus 13 through the element And 85 on the bus 109 subscriber-receiver.

Simultaneously with the GI signal, the receiver outputs the HH signal and other necessary control information (nominal information, which are output from the node 22 (Fig. 11) of block 1. via the signal lines of the information signal bus 13 to the input 4 the switch 27, where the exchange control signals are fed to the inputs of the And 49 elements opened by the level 1 signal from the output of the flip-flop 46.

The signal from the receiver and other exchange control signals of the receiver (with the exception of the signal UE) from the output of the corresponding elements And 49 directly appear on the signal lines of the information signal bus 12. The signal of the relay is entered in block 1 ;; to the input of the node 22 (Fig. 10), where it arrives at the input of the element And 78, open-r6 with a signal of a single level from the output35

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the incoming bus 13. On the bus 13, the signal UE enters the block 4 (FIG. 4), to the signal inputs of each of the switches 27 (FIG. 5), where it arrives at the inputs of the corresponding And 49 elements.

Element And 49, on the same input of which there is a signal with. level 1 from the output of the corresponding trigger 46, will provide a UE signal to the input of one of the elements OR 53, the output from which the corresponding trigger 54 will be set to one, the signal from the output of this trigger is output to the input element And 55. At the remaining inputs element 55 And also there is a signal with level 1, since the signals of the zero level from the outputs of the other triggers 46, not participating in the switching of subscribers, are inverted by the corresponding elements NOT 51, the signals from the outputs of which through the corresponding element you OR 53 mounted sootvetstvuk que triggers 54 into a single state. The signals from the outputs of these triggers are assigned to the inputs of the element 55, If the source is connected to at least one

yes, trigger 74. The command Exchange with the processor, which enters node 22 via line 8 at the input of element I 80, establishes trigger 79 into a single state.

As a result, the signal from the receiver through the element And 78 is transmitted to the bus 108 and is brought to the subscriber-source. In this way, information exchange control signals are exchanged between the source and the processor.

Information exchange between block 1

source and receiver unit 1 (processor) does not differ from the exchange control signals exchange, since the exchange control signals and signals are transmitted on the same buses (12, 13), but on different lines

these tires. After receiving the next information block (byte, word), the receiver generates a signal. UP, indicating readiness for

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the incoming bus 13. On the bus 13, the signal UE enters the block 4 (FIG. 4), to the signal inputs of each of the switches 27 (FIG. 5), where it arrives at the inputs of the corresponding And 49 elements.

Element And 49, on the same input of which there is a signal with. level 1 from the output of the corresponding trigger 46, will provide a UE signal to the input of one of the elements OR 53, the output from which the corresponding trigger 54 will be set to one, the signal from the output of this trigger is output to the input element And 55. At the remaining inputs element 55 And also there is a signal with level 1, since the signals of the zero level from the outputs of the other triggers 46, not participating in the switching of subscribers, are inverted by the corresponding elements NOT 51, the signals from the outputs of which through the corresponding element you OR 53 mounted sootvetstvuk que triggers 54 into a single state. The signals from the outputs of these triggers are assigned to the inputs of the element 55, If the source is connected to at least one

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the receiver, at the output of the element OR 52, there will be a signal With a level of 1 which also enters the input of the element AND 55. Therefore, the element And 55 is open and the signal UE from its output is passed through information-signal bus 12 into block 1. At the same time, the signal UE with element output 55 is assigned to the inputs of the flip-flops 54 and resets them.

A pulsed signal UE via bus 12 enters the source unit 1 (Fig. 1) to the input of node 22 (Fig. 10), passes it through the transit and via the signal bus 108 is brought to the source subscriber. Upon receipt of this signal, the source can supply the next block (byte, word) of information.

After the exchange of information is completed, the source detects a pulsed KP signal, which, by its signal one, does not appear in source block 1 at the input of node 22 (Fig. 10). At node 22, the signal KP resets the trigger 74, thereby ensuring the removal of the GI signal from the bus 12 and the possibility of supplying the source (GI signal) through the AND 76 element along line 1 1 to blocks 2 and 3, resets the trigger 79, which prevents the signal from the bus through the bus 108 to the source subscriber and through the information signal bus .12 is sent to the input of the switch 27 (FIG. 5), where the signal KP from the bus 12 through the corresponding element 48 through the bus 13 is sent to the receiver unit 1. In addition, in switch 27, the signal KP is flattened to the inputs of the elements OR 47, the output of which provides the reset of the triggers 46 and, consequently, unmasking the information signal lines 12 and 13 without the processor.

On line 34, the signal KP is entered into register 32 (FIG. 4) at the input of one of the elements OR 64 (FIG. 8), the output of which is reset, trigger 65, with the command

Source number ... to transfer information

was set to one.

In receiver unit 1, the signal KP is input to node 22 (FIG. 11), where it flushes trigger 86, which prohibits reception from the source through element 85 of the GU signal, resets trigger 81, thereby ensuring that the receiver can

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from the bus 109 applications for servicing -, (-GY signal) through the AND 83 element via line 1l to priority block 2 and interrupt block 3.

In addition, in block 1 of the source (Fig. 2), the trigger signal 113 resets the trigger 113, thus preventing the source information from being transmitted to the bus 12, since the AND 23 elements are closed with a zero signal from the trigger 113 output.

At the end of the exchange, processor 7 enters Block 5 with the command End of Exchange. In block 5 (FIG. 3), the decoder 26 generates a command enable signal and issues a command to Continue to view the wok on bus 10. The command and the enable signal on buses 10 and 8 arrive at blocks 2 and 3. In block 3 (Fig. 12), the command and enable signal are sent to the input of the element 110, the unit level signal from whose output trigger 106 is set to one, allowing thereby, the pulses from the GI 105 through the element AND 104 to the counter 103. Thus, the block 3 resumes viewing of the application.

The exchange of information on the second path is carried out as follows. Processor 7 sends the command to Source No. ... transmit-information. In this case, the command indicates the number assigned to the processor. The bus 10 team leads to blocks 4, 2 and 3.

The passage of information on the bus 9 is blocked by the decoder 26. In block. ke 4 team arrives at node 30 (Fig. 4). Further execution of the command is similar to the implementation of it when exchanging information on the first path.

The command for Receiver No. ... (for receivers No. ...) to receive information is performed in the same way as executing it when exchanging information on the first path. In addition to the command, the command via bus 38 from the output of node 30 is input to the register 31, where it establishes the corresponding triggers 62 (Fig. 7). The command Exchange with the processor is communicated to the subscriber-receiver through its block 1.

In this case, the command is input to the node 22 and is executed in the same way as executing it when exchanging information on the first path.

Command completion The end of the exchange is described in the picture.

The exchange of information on the third path in accordance with the first exchange mode is occ ec ecl ec as follows.

The source subscriber exposes a service that goes to the processor 7 in the same way as it happens when exchanging information on the first path.

Having received from subscriber number 3 the subscriber requiring service, processor 7 executes a command to read the state of receivers, which enters block 5, where it is allocated by node 24 (Fig. 3) and arrives at node 25 and the decoder 26, forms a command and a signal to allow passage the commands at the output of the decoder 26. The command enable signal and the command, respectively, on buses 8 and 10 are received in block 4 at node 30 (Fig. 4). Through node 30, the bus enters register 31 via bus 40. If any receivers required by the source at a given time are in the state of exchange with another source, then at the processor command Receiver No. ... (receivers No. ... ) to receive the information received by these receivers from the node, 30 (Fig. 4) via bus 38, in register 31 (Fig. 7), this command caused the corresponding triggers 62 to be set to one. In register 31 (Fig. 7), the command To read the state of the receivers goes to the elements And 63, where the opening of the corresponding element occurs. Enta I. Information from the flip-flops 62 via the bus 44 enters the bus 13 of the processor and is brought to the processor 7. The processor 7, having received information about the status of the receivers, analyzes the state required by the source of the receiver (s) and determines whether it can work with it source at a given time.

Taking into account that the sources in the system can simultaneously be receivers of information (for example, computers), in this case processor 7 forms the command Read sources state. The command enters the block 5, where the node 24 (Fig. 3) is allocated, and appears on the node 25 and the decoder 26. The decoder 26 forms

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the command and exposes it to the bus 10, simultaneously generates a command enable signal and exposes it to the bus 8. The command and command enable signal, respectively, on buses 10 and 8 go to node 30 (FIG. 4). If any receivers required by the source are currently sources in exchange with other receivers, then at the command of the processor, Source No. ... transmit information received by these subscribers from register 28 via bus 33, corresponding triggers of register 65 (Fig. 8) were set to one. The command to read the state of the sources through the node 30 via the bus 41 is transmitted to the register 32, where it enters the elements AND 66 (FIG. 8) and allows the information from the triggers 65 to pass through the bus 43 to the processor bus 13 to the processor 7. -in that information. IF receivers are busy, then process 7 stops servicing this application. If the receivers are free, processor 7 generates a command to Source No. ... to transmit information, which is processed in the same way as it happens when information is exchanged along the first path. The processor 7 then instructs the receiver No. ... (receivers No. ...) to receive information, which, like the command to Source No. ... to transmit information, is output to blocks 1 of the receivers, but the decoder 21 ( Fig. 2) generates a signal permitting the reception of information on the register 20, and a signal prohibiting the passage of the application of the subscriber-receiver through the node 22 via bus 11 to blocks 2 and 3.

The Interchange command enters block 5 (Fig. 3), where it is allocated by node 24 and fed to node 25 and decoder 26. As a result of deciphering the Interchange command, the command from block 25 is blocked from being sent to bus 9 and issued to line 8. In addition to In addition, the decoder 26 generates the command Continue to browse the request and a signal to allow its passage. This command on bus 10 and the command enable signal on bus 8 is output to blocks 2 and 3 (Fig. 1) and performs in the same way as executing a command when exchanging

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not on the first path. The Interchange on line 8 command (Fig. 1) is available to all blocks 1, but is brought only to unit 1 of the subscriber-source and blocks 1 of the required subscriber-receivers through the node 22 of the source block 1 and the nodes 22 of the blocks 1 of the receivers, the command is executed similarly command execution - Exchange with the processor when exchanging information on the first and second paths.

The exchange of information on the third path in accordance with the second mode of exchange of information is carried out as follows.

. The input comes from the source to the processor in the same way as it happens when information is exchanged along the first path.

The processor issues a command to Source No. ... to transmit information, which is executed in the same way as executing it when exchanging information on the first path.

 The processor then sends the command to receiver No. ... to receive information, where the number assigned to the processor and the command Exchange with procedure are specified as the number of the receiver. Both commands are executed in the same way.

executing them in the exchange of information on the first path.

one .

In this case, the processor receives from the source a control word, the rum contains the numbers of receivers required by the source. The processor then forms the command Source No. ... to suspend the exchange. The command through block 5 via bus 9 enters block 4 and from it via bus 14 into block 1 of the corresponding source. In block 1, the command arrives at the decoder 21 (FIG. 2), which generates a signal at the input of the trigger 113 and resetting it, thereby preventing the source from sending information to the bus 12 through the AND 23 elements. produced by the decoder 21, falls to the signal line

.KP informational signal bus 12 and, similarly to the signal KPus, there is a disconnection of the information and signal sources and busses. the processor and resetting the trigger to fix the source state in register 32 of block 4.

The processor then generates commands to read the state of the receivers, read the state of the sources, analyzes the information received and, if the receivers are not able to receive the information, further service of the application stops and can be resumed after the source is issued the service request in blocks 2 and 3.

If the receivers are able to receive information, then the processor 7 generates commands to the Source No. ... to transfer information, to the No. ... receiver (to the No. No. receivers) to receive information to the Interchange command.

The first two commands are executed in the same way as exchanging Q information on the second path, the Interchange command is executed similar to executing it when exchanging information on the third path in accordance with the first exchange algorithm. Subsequently, the processor does not participate in the exchange of information and is ready to serve the next request, the exchange is controlled by the source.

If the source is exchanged with a group of receivers, then the switch 27. Unit 4 generates a unified receiver control signal from private control signals received from each switched receiver.

 In the switch 27 (Fig. 5), the partial signals UE from the switched receivers on the buses 13 through the corresponding elements AND 49 and the elements OR 53 set the corresponding triggers 54 to one state. The rest of the triggers of this group are also set to one by the inverted zero-level signals from the outputs of the flip-flops 46, which do not involve 1X in the switching of subscribers. Since there was a switching of subscribers, at the output of the elements OR 52 and, therefore, at the input of the element And 55 there is a signal with level 1.

As in the general case, private UE signals from receivers arrive at different points in time and, therefore, the triggers 54 also set 0

five

0

five

0

55

at different points in time, a single level signal at the output of the And 55 element (a single receiver control signal) can only occur upon receipt by the switchboard 27

nineteen

private signal UE from all connected subscribers. A single control unit of the receiver from the output of the element 55 through information signal bus 12 is entered into the source unit 1 and brought to the subscriber via bus 109. At the same time, a single receiver control signal ensures resetting of the flip-flops 54 (FIG. 5).

Claims (1)

Invention Formula A device for exchanging information between a processor and subscribers, comprising a group of communication units with subscribers, whose I / O groups are device I / O groups for connecting subscriber information and control I / O groups, first priority block and interrupt unit the request inputs of which are connected to the first outputs of the request of communication units with subscribers of the group, the address inputs and the first informational inputs-outputs of which are connected respectively to the first output of the address decoding unit, and commands and the first information group of inputs and outputs of the switching unit of information and commands, the first permitting input of which is connected to the enabling inputs of the priority block and interrupt unit and the second output of the address and command decryption unit, the third output of the priority block and information switching unit and, commands, first 14 23 and bit of information 91 AND. The magnitude of the information issued by the processor on the bus 15 . 93 And the command difference is external abo nentam 45 And the number of subscribers-receivers 46 Tr Number of subscribers-receivers 1444792 20 five 0 five 0 five whose information input-output is the input-output of the device for connecting to the information input-output of the processor, the output of the priority block, the first and second outputs of the interrupt block are connected respectively to the first and second information and control inputs of the switching unit, the output of which and the second output the interrupt block are the corresponding outputs of the device for connecting to the input of the request address and the input of processor faults, the input-decoding block of the address and commands, the command inputs of the interrupt block and the priority block are connected to the input of the device for connecting the information output of the processor, characterized in that, in order to improve the performance of the device, the second groups of the request inputs of the priority block and the interrupt block are connected to the second outputs of the request of communication units with subscribers of the group, the inputs-outputs and command inputs of which are connected respectively to the second group of information I / O and the group of outputs of the switching unit of information and commands, the second permitting input of which is One with the fourth output block deshifraitssh addresses and commands, and second information input-output data and commands switching unit is vhbdom- output device for connection "command input-output processor. 211A4479222 Table continuation 23 98 99 102 NOT AND AND ////) 7 ///; ZHG / SHG / r / iv; L./g/ / y;  TZ (Yu tm) 1A44792 24 Continuation of the table The number of external subscribers Counter difference 106 17 12 (Pr, YU h / W .. 15 7 h / v ten AT 1 101 Figg s iO ". J i2 f P {Pr) Llzz 27 / 7 p 33 36 28 8 10 29 / U ( ) i2 (if -f-r -r 17 2i / Si E} 38 . 5i ifi / 59 J o y / 42 3 32. 43 ( /; f) Phie. QJtfiS - iv.6 7 one 9S /five AND 77 //; 77U / y ;; 5P7 - p-pntnl 98 Uh S9 :four 97 3 tl U Ucmoi f ufc 1- npaefiHU. Isayumik i- / Jpue HUK / I1 III I I acff70t / f uK2- / / Jue / iH 2 U.c / nowu / 2-- Hpue / HUfcz t Fi8. //