SU1357971A1 - Device for interfacing computer with computing system - Google Patents

Abstract

The invention relates to the field of computing and can be used to combine computers into a computer system with an arbitrary machine-to-machine link graph. The purpose of the invention is to increase the useful time of the computer in the system by reducing the machine downtime while waiting for operator intervention and reducing the number of manual operations for managing the system. Purpose dosso h

Description

13

is fraught with the fact that the device containing the tuning unit 10, the decoder 5 register addresses, the interrupt block 9, the first input registers 2-1, output 1-1, input status 4-1 and output state 3-1 , the priority block I1, the decoders 8-1, ..., 8-p input signals, the decoder 7 addresses of the console terminal, the decoder 6 addresses of the interface device, trig

one .

The invention relates to computing techniques and is intended to integrate a computer into a computing system, with an arbitrary machine-to-machine communication graph.

The purpose of the invention is to increase the useful time of the processing in the computing system by reducing the time of machine downtime, waiting for operator intervention and reducing the number of manual operations to manage the system.

1 shows a functional diagram of the device; FIG. 2 is a block diagram of the computing circuit of the fragment — FIG. 3 is a functional circuit of the tuner; figure 4 is a functional diagram of the priority block; figure 5 is a functional register register view; FIG. 6 is the functional register of the input register; Fig. 7 is a functional diagram of the status and input registers; FIG. 8 is a functional diagram of the descriptor. address register; figure 9 is a functional diagram of the console terminal.

The device contains output registers 1-1, ..., 1-p, input registers 2-1, ..., 2-p, registers 3-1, ..., 3-p output status, registers 4-1 , ..., 4-p input status, decoder 5 address of the register, decoder 6 device addresses decoder 7. addresses of the console terminal, decoders 8-1,.,., 8-p input characters, block 9 interrupts, block 10 settings , block 11 priority, trigger 12, p blocks 13-1, ..., 13-p elements OR, elements OR 14 - 16, element AND 17. Keys 18 and 19, input-you

ger 12, AND and OR elements from the second to the p-e (p is the number of inputs 24 and exchanges 23 of the exchange), input registers 2, output 1, input states of the 4 states of output 3, and the connection between them, allowing each computer to perceive code dressings arriving on the communication line from the neighboring computer, as commands issued by the operator from their own computer control panel. 9 il.

data run (buses) 20, input (bus) 21 addresses and input / output (bus) 22 controls, outputs 23-1, ..., 23-p exchange, inputs 24-1, ..., 24-p exchange , v. move 25 character code.

Virschslitelna. the system using the interface device may comprise a monitoring terminal 26, a computer 27 and the device 28 itself for interface the computer into the computing system.

Block 10 customize 11: a (FIG. 3) contains a decoder 29 setting, register 30 setting, a group of elements OR 31 and a key 3 2.

The register 1-i of the output (, ..., p) (FIG. 3) contains the element AND 33, the key 34, the element 35 of the delay and the register 36.

Register 2-i input (6) contains the register 37, the key 38, the element And 39, and the key 40 ..

Each register 3-i output state or 4-i input state (Fig.7) contains a key 41, an AND element 42, a key 43, a register 44 and a trigger 45.

The decoder 5 address register (Fig.8) is made on the decoder 46 and the elements And 47-52.

The priority block 1 (FIG. 4) is implemented on AND 53 elements.

The console terminal 26 (Fig. 9) contains a console terminal decoder 54, a register decoder 55, an output register 56, an input register 57, an output status register 58, an input state register 59, a display unit 60 and a keyboard input unit 61.

Output registers 1-g1, ..., 1-p are intended for storing and outputting character information on a machine-to-machine communication line via codes 23-1, .. ,, 23-p exchanges. The write signal to the register 36 from the output of the And element 33 is supplied via the delay element 35 to the exchange output 23 (line a, Fig. 5) as an input enable signal for the adjacent device for pairing.

The input registers 2-1, ..., 2-p are used to receive and store symbol information coming from the machine-to-machine communication lines to the 24-1, ..., 24 exchange inputs. Element 39 is used to form a read signal from the registry 37. The key 40 is designed to output the contents of the register 37 to the data buses 20. The signal to read out the register 37 arrives at the output of the exchange bus 24 as a sign of completion of the input.

Registers -3-1., ..., 3-p of the output states are intended for storing information about the output status of the 1,2, ..., p-th exchange direction, respectively. The key 43 is designed to output the contents of the register 44 to the data bus 20.

The trigger 45 is set by a signal from output 23 (line b, 6 and 7), coming from an adjacent interface device when it finishes entering information to it.

The 4-1, ..., 4-p input status registers are intended to store information about the input status 1,2, ... of the exchange direction, respectively. The installation of the trigger 45 is ready for input in these registers 4-i by a signal from input 24 (line a, Fig. 5).

The decoder 5 address of the register is used to generate signals to read (write or write) to the registers of the device. The resolution of the register address decoder 5 is developed with the address decoder device 6 and the console address, terminal 7. The output signals from the outputs of the decoder 6 and 7 are fed to the input of the address decoder 5 through the OR element 14 and the AND 17 element The executive signal is generated One of the corresponding outputs of the decoder 5 address of the register on the signals Enter or Vshod, coming from the computer via the bus 22 control. The structure of the decoder 5 address register includes

de-ga 46 and AND 47-52 elements that generate write and read signals to device registers.

The decoder device addresses 6 is used to decipher the addresses of the device registers. The signal from the output of the descrambler 6 permits the operation of the decoder 5 of the register address when accessing the registers of the device for interfacing from a computer.

Decoder 7 address of the console terminal serves to decipher the addresses of the console console registers. The signal from the output of the decoder 7 enables the decoder 5 to work from the computer 27 to the registers of the console terminal 26. The signal of the decoder 7 through the element 17, which opens the signal of the logical unit from the forward trigger output 12, and through the element OR 14 enters the input of the decoder 5 address register. In this case, the address decoder 5 addresses the access to the data registers and the keyboard status of the console terminal from the computer and interprets it as accessing the input registers and the input state, and the access from the computer to the data registers and print status of the console terminal is interpreted as access to the registers and no status.

We show the purpose of the decoders 5 - 7 for example.

The registers of the console terminal of the Electronics-60 computer console are as follows:

177560 - keyboard status register (input) j

177562 - keyboard data register (input), 177564 - print status register

177566 - print data register

(code).

The addresses of the device registers for pairing are as follows:

1677X0 - input status register,

1677X2 - input register,

1677X4 - output status register,

1677X6 - the register of the code

X - position of the address code,

identifying number 1,2, ... ..., p (: & 7) of input 23 or output 24, respectively.

The position X of the address code is decrypted by the configuration decoder 29 of the setting unit 10 and in the positional code C 1 is written to the setting register 30.

The register address decoder 5 determines from the contents of the low bits of the address bus 21 of the register type (input, input input output state, output state) that is being addressed.

The decoder 6 of the device address selects from the computer the addresses of the device registers from the contents of the higher bits of the address 21 bus. The signal at the output of the decoder 6 occurs when the address 1677X appears on bus 21.

The decoder 7 of the console terminal address accesses from the computer to the registers 56 - 59 of the console terminal. The signal at the output of the decoder 7 is generated when the address 17756 is received on bus 21.

The decoders 8-1, ..., 8-p input symbols are used to select from the input character information the symbol of the device transfer to the console terminal control mode and the symbol for exiting this mode.

Upon receipt of the machine-to-machine communication line in the 5-way register of one of these symbols, a signal is produced at the corresponding output of the decoder. These signals are used for

Setting the state of the trigger 12.

Block 9 of alarms generates alarms for input into the computer or output from it of the next character at the corresponding output 23 or input 24. Interruption occurs when the ready register of the corresponding device register is set and there is permission to terminate from the computer. Interrupt signals are received by the computer via the control bus 22, and the cut vector is transmitted via the data bus 20. A: The setting unit 10 (FIG. 3) serves to determine the direction of the exchange with the neighboring computers of the system. The tuning code comes from the computer via the bus 21 ad-. and is converted into the position code of the exchange direction number (1, 2, ..., p) with the help of the decoder 29 settings. The exchange direction is recorded. In register 30 of the setting, when a signal arrives at key 32 from the output of the decoder 5. Another source of the building code is block 11 of priorities. From the outputs of the priority block I1, the position code of the direction number enters the setting register-30 through the element group OR 31.

. ,)

The priority block 11 (Fig. 4) serves to allocate the highest of the control requests from the neighboring computers 27 of the system. Management Requests

are produced by neighboring machines, either in response to signals that the computer under consideration 27 goes into stop mode, or when the next computer 27, on its own initiative, puts the computer 27 into stop mode. Since the neighboring computers 27 operate independently and autonomously, it is possible to simultaneously receive control requests to this machine from several neighboring computers 27. The highest of the incoming requests is allocated as a positional code at the outputs of the block

11 priority. The value of a logical unit is generated only in one code, for example, at an output, for example at code i, if and only if a single signal arrives at the i-th input of priority unit 11 and there is no single signal at any of the outputs to the left of (FIG. four). Trigger

12 serves to enable the decoder 5 address of the register, which generates read signals (write to input registers) of the output when accessing the computer 27 to p €; the console terminal mist 26 and issue a stop signal of the computer when control requests are received at the initiative of neighboring computers 27. When This signal of the logical unit is generated at the output of trigger 12 according to the request signals received from the first outputs of the decoders 8-1, ..., 8-p input symbols. The stop signal enters the computer 27

bus 22 control. The installation of a logic zero signal at the second output of the trigger 12 is effected by signals from the second outputs of the decoders 8-1, .., 8-p input symbols or a signal

Reset control bus 22. When the computer enters the stop state, the logic zero level at the first output of the trigger 12 blocks the operation of the control device of the control terminal of the given machine (the And elements 19 are closed at the first input). When the computer 27 executes the program, the level of the logical unit from the first output of the trigger 12 permits the operation of the computer 27

with console terminal 26 to the addresses assigned to its registers.

Input and output occurs under computer control and are carried out using its RAM.

In the program mode of the computer, the device operates as follows.

When entering from machine-to-machine communication lines, information is fed to inputs 24-1, ..., 24-p and entered into registers 2-1, ..., 2-p.

In the respective registers 4-1, ..., 4-p of the input state by a signal from input 24, a readiness trigger 45 is set for input into a computer (Fig. 7). The signal from the trigger output 45 to the input enters the data bus 20 and block 9 interrupt. Entering information from the input register into a computer can be carried out both when the program detects the presence of a readiness sign to enter the state 4 of the input state (the so-called flag polling mode) into the contents of the register, as well as when the service is processed. input readiness signal (input mode by intervals)

When performing the procedure of counting from the register 2-i of the computer input, the code on the bus 21 of the address is the code corresponding to the address of the register 2-i of the input and the pulse signal. The decoder 6 of the address of the device generates a signal permitting the operation of the decoder 5 of the register address. The permission signal through the element OR 14 is fed to the third input of the decoder 5. From the fourth output of the decoder 5 of the register address to the second inputs of the input registers a signal is received. The number i (, 2 ... p of the register to be addressed is determined by the setting unit 10 by decrypting certain bits of the address code. From the output of the setting unit 10, the third input of the input register 2-1 receives a work enable signal Register i-ro. The read and enable signals of the i-ro register arrive at the input element AND 39 (FIG. 6) ...

The contents of input register 2-i are output to data bus 20. Signal sci; tshani the contents of the i-ro input register resets the trigger 45 ready to enter in the register 4-i state

input (Fig.8). The flip-flop 45 is reset when the input 42 of the input state, which is part of register 4-i, receives the output signal of the decoder 5 and the operation enable signal from the output of the setting unit 10.

The trigger 45 is set by a signal received from the input 24 at the moment of recording information from this input into the register 36. The input from the input registers 3 and 4 and i is entered in the same way as described from the input register.

In case the trigger 12 is set, then the contents of the input registers 2-i and the registers 3-i and 4 -i of the input state and the output are read when the addresses corresponding to the registers of the console terminal 26 are set from the computer 27 to the bus 21.

When the output from the registers 1-1 ,, .., 1-p output to the outputs 23-1, ..., 23-p receives the contents of the registers and the write signal to the register (line a, figure 5)

The recording of the output information of their computer into the register of the code is carried out as follows. The address of the register into which recording is made is assigned to the address bus 21 from the computer 27. The register is sampled similarly to the procedure described for input using decoders 5-7 and the decoder of block 10. The signal from the second output of the decoder 5 of the register address and the signal from the i-ro output (, 2, ..., p) of the postunshot setting unit 10 element 33, allowing recording in register 36 of information on buses 20. Trigger 45, which is part of register 3-i of the output state, is reset by signals coming to element 42 (Fig. 7) from the output of the decoder 5 and block 10 settings. The trigger 45 is set by a signal from output 23-1, ..., 23-r. This signal is generated when information is output from the output register to output 23. The output signal from the trigger 45 enters the interrupt block 10. The trigger 45 is part of the register contents 3-i states of the output, i.e. its state can be interrogated from a computer while reading the contents of the high status register.

The recording of information from the computer into the registers 3-i, A-i of the status of the input and the input is made similar to the recording of information from the computer into the registers of the output.

Consider the process of exchange between neighboring computers connected via devices 28 by connecting the code 23 of one device 28 to the input 24 of another. When writing information from the computer 27 to register 36 of register 2-i output at output 23, the contents of register 36 and the recording signal ( lines, a, Fig. 5) into the register. The delayed time, which ensures the end of the recording in register 36. The signals that write to register 36 are reset via AND 42, trigger 45, which is contained in state register 3 i. The information from the output 23 is fed to the input 24 of the neighboring one. device 28. The recording signal (line a, 6) allows entry of the contents of the register 36, which is fed to the input 24, into the register 37 through the key 38. In addition, the recording signal is fed to the input of the trigger setup 45, the register 4-1-state neither the input of the adjacent device 28 (line a, Fig. 8). A neighbor computer.27, after determining the presence of a readiness signal for input, produces a jitter of the contents from the input register. Signal to draw out with on the element And 39 (line b, 6) This signal allows the input of the contents of the register 37 to the data bus 20, is fed to the input 24 and to the output 23 of the neighboring computer 27, from which it sets the trigger 45 to the output (line b, fig-7). ; . The computer 27 can carry out the next output to the next computer 27.

If the computer from the program mode of operation has switched to the stop mode, the interface device sends a stop symbol to all neighboring computers. 4 Stop

The formation and output of the symbol of the stop are as follows. The stop signal of the computer via the control bus 22 is fed to the control input of the key 18. The information input of the key 18 receives the symbol 4 Stop, which is permanently located at the input 25. From the output of the key 18, the Stop symbol is entered into all the registers of the 1st to the output, from where output to the machine communication link.

Neighboring computers 27, which have terminated the symbol as usual symbolic information, are switched to the execution of the corresponding processing program. Using the described output process, they send the 27 characters of the request to control the computer in the remote mode to the stopped neighboring computer

ulta These characters are extracted by the 8-rl decoders. . . , 8-p input computers stopped the computer. The direction from which the control request is received is recorded in register 30

settings. The decoders of the input symbols, which have inserted the request symbol from the input information, generate signals arriving at OR 15 at the first input of trigger 12 and at the inputs

priority block. These signals at the second output of the trigger 12 sets the signal of the logical unit ,. which corresponds to the transfer of the interface device to the use mode

its registers as registers; console terminal. In this case, the signal of the logical unit from the second output of the trigger 12, which enters the first input element I 17, passes the signal from the output of the decoder 7, which is output when the x terminal 27 registers from the computer 27 to the third input of the decoder 5 ad-, race register. Logical signal

the zero from the first output of the trigger 12 closes the key 19, prohibiting the receipt of the contents of the address bus to the console terminal 26 (if any), connected to the computer 27, which has entered the stop mode.

The operation of the console terminal circuits is enabled when trigger 12 is set to the zero state. At the same time, information from the busses 21 goes through the elements I open with the trigger 12 and to the decoder 55. The latter provides the read signals (records from the buses 22 to the register 56 - 59) indicated by

; code on the bus 21. When installing the trigger 12 in one state, the flow of information from the bus 21 to the console terminal 26 is prohibited: the elements And are closed. In this case, the operation of the register address decoder 5 is permitted, which provides access to registers 1-4 of device 28 when issuing register addresses of a console terminal to buses 21. Thus,

There is a substitution of the registers of the console terminal .26 registers of the device 2

The information coming from the stopped computer 27 and addressed to its console terminal is transmitted to the next computer 27 indicated by the contents of the setting register 30. Neighboring computer 27 receives and processes received information. In accordance with the processing program, the neighboring computer 27 transmits along the communication line to the computer stopped the symbolic information, which is perceived by the latter as commands of the keyboard of its console terminal, the computer 27, which controls the stopped computer 27, or executes the program simulating the operation of the console terminal operator or sends the received information to the operator at the monitoring terminal connected to it, and the commands received from the operator are transferred to the stopped computer 27.

During asynchronous and independent operation of neighboring computers, the request symbols for control in the remote control mode can enter the device 28 of the stopped computer at the same time, the Priority block 11 selects the most senior of the simultaneously received requests (or the first request of the time) and write the position code to the register 30 of the settings addresses of the machine-to-machine communication line from which the elder from. requests.

Thus, the character information received from the direction recorded in the setting register 30 is entered into the computer operating in communication mode with the console terminal as commands from the keyboard of the console terminal. The characters entered from the computer into the console terminal are entered into the register 1-i of the output and output into the communication line. The i number of the output register 1-i is determined by the setup register code.

The transition of the stopped computer to the program operation is carried out by receiving from the computer, which functions as a console terminal, through a special machine / computer communication line, which is a command of the console terminal. This symbol is allocated by the decoders 8-1,., .-, 8-p input symbols of the stopped computer and is fed to the inputs of the element OR 16, the output of which is connected to the second input

ten

20

25

You is 35797112

trigger 12. The latter is reset. The output from the control mode from the remote PT can also be performed when the signal is higher. The computer is reset via the control bus 22 to the input of the OR 16 element or when the corresponding switch of the control panel of the base computer is pressed.

The proposed device for matching -. the computer allows you to compile a computer system with an arbitrary number of machines that have possibly different (from 1 doc) number of connections with neighboring computers; have an arbitrary number in the system (from one up to the number of machines in the system) of peer terminals, each of which, independently of the others, can be used to control any machine of the system, which increases the fault tolerance of the system. Figure 2 shows a fragment of a computing system of six computers, of which only three have a terminal.

Each computer of a computer system, working under program control, can put any neighboring computer into shutdown mode. For this, she sends her a special code dressing. In this case, the computer, having switched to the stop mode, perceives the information coming from the machine in question as commands from the console terminal. When the computer spontaneously goes into a stop state, a special signal (stop code) is sent to all the computers next to it, the switch 4Q sachet these computers to the appropriate. processing program. Thus, the hardware of the proposed interface provides the implementation of two fundamentally necessary mechanisms for organizing an auto-; mathematical control of the computing system: the ability of one machine to act as a GHG in relation to another neighboring one; notification of cQ by each machine going into stop mode (communication with the console terminal of the machine 3, neighboring machines about this event. On the basis of these instrumental means, software can be built to allow one machine to be controlled from another by a chain of transit machines located between them. The specified software should perform

thirty

35

routing and information between machines, provide initial loading of programs into machines, etc. The possibility of building such software has been considered in the literature. With such software, it is possible, after transferring the existing software to one of the computers (from a console terminal connected to this computer), to provide automatic (software) control of all other computers of the system. In this case, the volume of operational operations for managing the system does not depend on the number of machines in the system. The ability of one computer to perform in relation to another function of the PT allows, without the operator’s participation, to poll and change the contents of the registers and memory cells of the neighboring computer, start programs in it from the desired address and any other actions that imitate the work of the operator and are provided for of her own console terminal.

The ability to notify all neighboring computers about the transition of the machine to a shutdown state increases the fault tolerance of the system, since the probability of a simultaneous failure of all neighboring computers is small. This property also allows the computer to automatically restart when the computer is malfunctioning or in emergency situations leading to its transition to the stop mode.

Any computer can control other computers that are not its neighbors. Control is exercised through a chain of transistors located between them.

Claims (1)

Invention Formula A device for interfacing a computer into a computer system containing a tuner, a register address decoder, a breakout unit, the first input registers, input states, output and output states, three OR elements, information inputs / outputs of the first input status registers and the output, the output of the first input register and the output of the interrupt block are connected to the input 5g output of the device data, the information inputs of the register address decoder and the configuration block are connected to the input of the device address. The first output register output and the information input of the first input register are the first code and the device data exchange input, respectively; the output attribute of the first register register record is the first output of the device exchange enable, the first input of the same name and with installation entrance the readiness attribute of the first register of the input status, the output of the read attribute of the first input register is the first output of the exchange of devices. -i the first homogeneous input of which is connected to the input of the readiness indication of the first register of the status register, tl and 0 that, in order to increase the useful time of work in a computer in a computer system by reducing machine downtime while waiting for operator intervention and reducing the number of manual operators for managing the system, a decryption is introduced into it the address controller of the console terminal, the address decoder of the interface device, the input decoders 0 characters, where p is the number of exchange directions, priority block, trigger, two keys, p blocks of OR elements and AND element, output of the k-ro register of the output, and information input of k-ro The input register c (, ..., p) is the kM output and the kM input of the device data exchange, respectively, the output of the record attribute of the k-ro register of the year is the kth output of the device exchange resolution, the .kth input of which has the same name connected to the input entry of the first input register and to the setup input of the readiness attribute of the k-ro register of the input status, the output of the counting sign of the k-ro input register is the k-th output of the device exchange completion, the k-th single-name input of which connected to the input of the installation sign of readiness 0 k-ro of the status register, the first output of the register address decoder is connected to the record input of all the register registers and to the reset inputs of the sign of readiness of all the registers 5 of the output state, the second output of the register address decoder is connected to the exchange control inputs of all output status registers, the third output of the register address decoder is co-; 15 dinene with inputs for all the input registers and reset inputs for all input status registers, the fourth output of the register address register is connected to the exchange control inputs for all input status registers, information input-output kx registers and codes kx input registers connected to the input-output data of the device, the output of the n-th input register (, ..., p) is connected to the information input of the n-th decoder input character, first and second output - 15 output address of the console terminal 20 the device, the information input of the first key is the input of the device stop symbol, the outputs of readiness signs of the status register and the input state are connected to the information inputs of the interrupt unit whose control input-output, the inputs of the register address decoders, the console terminals of which are connected to mi inputs of the second and third elements OR, respectively, the outputs of which are connected to the inputs of the installation and reset of the trigger, the direct output of which is connected to the synchronization input of the priority block and the first input of the AND element, the output of which is connected to the first input of the first OR element, the output of which is connected to the strobier 25 and device for pairing and inserting the register address decoder and swarm control input of the first key of the tuning block, the nth output of which is connected to the inputs of the chip select n-X input registers, input state, output state and output state, the first The output of the n-th decoder of the input symbol is connected to the information input of the n-th bit of the priority block, the output of which is connected to the input, which transform the control input-output of the device, and the output of the first key is connected to the first inputs of all blocks of OR elements, the second inputs of which are connected with the input-output data of the device, the output of the n-th block of elements OR is connected to the information input of the n-th output register. u 797116 In the configuration unit, the information inputs of the second key, address decoders of the console terminal and the interface device are connected to the device address input, the output addresses of the interface device address controller and the console terminal are connected to the second inputs of the first OR element and the AND element, respectively, the inverse output trigger is connected to the first control input of the first key and to the control input of the second key, the output of which is the device, the information input of the first key is the input of the stop symbol of the device, the outputs of readiness signs of the status register and the input state are connected to the information inputs of the interrupt unit whose control input-output, the inputs of the register address decoder, the console terminal and the interface device and the second control input of the first key is the mate and interface devices and the second control input of the first key the control input device output is developed, and the output of the first key is connected to the first inputs of all blocks of OR elements, the second inputs of which are connected to the device data input-output device, the output of the n-th block of OR elements is connected to the information input of the n-th output register. FIG. g g 29 fN / J .. FIG. 20 36 -lt23 fj Sxod 6 ft6 i 2 3 " Bibiod BSod il22 7 fS 1st byV "five Z-u Sbijrod 5t LI J-tf 6v1 od 52 if-and exit S-th byhoZ Fig.c Compiled by A.Ushakov Editor N. Bobkova Tehred L. Serdyukova Proofreader S. Cherni Order 6000/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., D.4 / 5 Production and printing company, Uzhgorod, Projecto st., 4