SU1439575A1 - Device for comparing numbers with tolerances - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to enhance the functionality by balancing the codes. The device contains a pulse generator t, a comparison block 2-5, a control unit 6, an analysis unit 7, subtractors 8, 9, registers 10.11, counters 12.13, And 14-17 elements clock input 18, initial setup input 19 , the inputs of the first 20 and second 21 compared numbers, the inputs of the setting of the capacities of the first 22 and second 23 counters. The function of the device is to achieve the equality of the number stored in the meter 12.

Description

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The invention relates to automation and computer technology and is intended for use in radio spectrometry.

The purpose of the invention is to enhance the functionality by balancing the codes.

Figure 1 presents the scheme of the device; figure 2 - block diagram ana

Liza; FIG. 3 is a control block diagram.

The device contains a pulse generator 1, comparison blocks 2-5, control block 6, analysis block 7, counters 8 and 9, registers 10 and 11, counters 12 and t3, AND elements 14-17, clock input 18, initial setup input 19 , the inputs of the first 20 and second 21 compared numbers, the inputs of the setting of the capacities of the first 22 and second 23 counters,

Block 7 analysis contains the elements And 24, and the element OR 25, - 25D.

The control unit 6 contains a register 26, elements AND-NOT 27, elements AND 28 - 31, elements OR 32 - 37, elements NOT 38 and 39, drivers 40 - 42 pulses.

The function of the device is to achieve equality (equilibrium) of the number stored in the counter 12 (13) with the number previously recorded in register 10 (11) by changing the contents of the counter 12 (13) to ± .1 least significant bit. The pulses controlling the counters 12 and 13 can be used by controlling inertial objects.

The device works as follows

Registers 10 and 11 record the numbers X and U. which are compared by blocks 2 and 3 of the comparison, respectively, with the numbers X and Y, stored in the counters 12 and 13.

The subtractors 8 and 9 calculate the values of -and | UV-V | which are compared by blocks 4 and 5 compared with the values of N, 2, / 2 and N, j / 2 (N, 4, the capacity of the counters 12 and 13), which are fed to the inputs 22 and 23.

Based on the results of the comparison, the analysis unit 7 determines, in which direction the contents of the counters 12 and 13 should be changed. In this case, it is determined whether, for the purpose of speeding up the balancing process, to go through the extreme 0

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The counter 12 is broadcasted 13. At the output of the analysis block 7, a signal is generated at one of the BoobKBt outputs, indicating the direction of change in the contents of the counters 12 and 13. The control block 6 generates control signals to the inputs of the AND elements 14-17, as a result, pulses from the generator 1 are fed to the summing or subtracting inputs of counters 12 and 13 in accordance with the chosen direction of balance.

Claims (1)

Invention Formula A device for comparing numbers with tolerances, comprising a generator and aIlco, the first and second comparison blocks, the first and second counters, the first register, six AND elements and the first SHS element, the output of the pulse generator connected to the first inputs of the first, second and third elements AND, the outputs of the first and second elements I are connected to the summing inputs of the first and second counters according to the first and second counters, the inputs of the first compared number of the device are connected to the information inputs of the first register, the outputs of which bits are connected with the first group of inputs of the first comparison unit, outputs Less, More and Equal to which are connected to the first inputs of the fourth, fifth and sixth elements, respectively, the outputs of the bits of the second counter are connected to the first group of inputs of the second comparison unit, characterized in that extending functional capabilities by balancing the codes, the first and second subtractors, the second register, the third and fourth comparison blocks, twenty-two AND elements, seven OR elements and the control block, with the second inputs The compared number of the device is connected to the information inputs of the second register, the outputs of the bits of which are connected to the second group of inputs of the second comparison unit, the input of the initial installation of the device is connected to the inputs of the first and second registers to the zero state, the outputs of which bits are connected to the first groups of inputs of the first and second subtraction respectively, the outputs of which are connected to the first groups of inputs of the third and fourth blocks of comparison, respectively, the second groups of inputs of which are inputs for specifying capacities of the first and second counters, the outputs of bits of which are connected to the second groups of inputs of the first and second subtractors, outputs of bits the first counter is connected to the second group of inputs of the first comparison unit; the output of the pulse generator is connected to the first input of the seventh element I, the outputs of the third and seventh elements I are connected to the subtracting inputs of the first and second counters, respectively; the output More than the first comparison unit is connected to the first inputs of the elements AND from the eighth to the sixteenth, the output Equals the first comparison unit connected to the first inputs of the seventeenth, eighteenth and nineteenth elements AND, the output is Less the first comparison block is connected to the first inputs of the elements And from the twentieth to the twenty eighth, the output More than the second comparison block is connected to the second inputs of the fifth, sixth, eleventh, twelfth, the sixteenth, nineteenth, twentieth, twenty-second and twenty-five elements And, the output Equals the second comparison unit connected to the second inputs of the ninth, fourth, twenty-first and twenty-sixth elements And, the output Less than the second comparison unit connected to the second inputs of the fourth, eighth , the tenth, the thirteenth, the fifteenth, the seventeenth, the eighteenth, the twenty-third, the twenty-fourth, the twenty-seventh and the twenty-eighth elements AND, the output of Not more than the third comparison block is connected to the third in odes sixth worn, ninth, tenth, eleventh, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh and twenty-eighth AND gates, vkod more third comparator block is connected to the third inputs of the four five 0 In addition, the twelfth, thirteenth, fourteenth, fifteenth, sixteenth, twentieth. Twenty-first, twenty-second and twenty-third elements And, No more than a fourth comparison block output is connected to the third inputs of the fifth and eighteenth and fourth inputs of the sixth, tenth, thirteenth, sixteenth, twentieth, twenty third, twenty-fourth and twenty-seventh elements And, Output More than the fourth comparison block is connected to the third inputs of the seventeenth and nineteenth and fourth and fourth inputs. The fourth, eighth, eleventh, twelfth, fifteenth, twenty-second, twenty fifth and the twenty-eighth elements AND, the outputs of the fifth, sixth, nineth, tenth, fourteenth, eighteenth, twenty-fourth and twenty-seventh elements of AND are connected 5 with the first inputs of the elements OR respectively from the first to the eighth, outputs of the fourth, twelfth, fifth, seventeenth , nineteenth, twenty-first, twenty-second and two, thirty-sixth elements And are connected to the second inputs of the elements OR, respectively, from the first to the eighth, outputs of the eleventh, sixteenth, twentieth and twenty fifth elements And connected to the third inputs of the second, fourth, sixth, and first elements, respectively, OR, outputs of the eighth, thirteenth, twenty-third, and twenty-eighth elements, AND connected to the fourth inputs of the second, fourth, sixth, and eighth elements, respectively, of the device’s clock input and second registers and control unit0 five 0 five 0 55 The outputs of the first and second comparison blocks and the outputs of the OR elements from the first to the eighth are connected to the information inputs of the control unit from the first to the tenth respectively, the first, second, third and fourth outputs of the control unit are connected to the second inputs of the first, third , the second and seventh elements And, respectively. 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