SU1437809A1 - Apparatus for checking wiring - Google Patents

Abstract

The invention relates to a measurement technique and can be used to test the insulation of electrically disconnected product chains, nagfimer in the power supply circuits of multilayer printed circuit boards, in the conductors of the cable and wiring harnesses. The purpose of the invention is to reduce the time spent on searching for de-rated circuits by optimizing the algorithm of the device operation. The device for controlling the installation contains 2.1-2.N check signal generation units, a decoder 3, the address register 4, a 5 cycle register, a multiplexer 6, a voltage source 7, a resistor 8, a control unit 9, keys 10 and 11 Start and Reset, a register 12 time control. Each block 2.1-2.N contains a state register 13, a state register 14, an OR element 15. An AND element 16. The switching elements 17, 18 and an indicator 19. The device also contains buses 20-24. The test signal generating blocks serve to excite contacts of the tested product 1 with voltage of different polarity from the outputs of the voltage source 7 for 1dikatsin contacts of circuits with defective insulation and for blocking the excitation of contacts in circuits with defective isolation from re-activation, 2 W-w., 1 tab. (L with

Description

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The invention relates to measurement technology and can be used to check the insulation in electrically disconnected circuits of products, for example, in the power supply circuits of multilayer printed circuit boards, in the conductors of cables and wiring harnesses.

The aim of the invention is to reduce the time spent searching for defective circuits due to the optimization of the device operation algorithm.

FIG. 1 shows a diagram of the device; in fig. 2 is a control block diagram.

Position 1 marked the checked product.

The device contains blocks 2.1-2, p forming the test signals, de- Encoder .3, register 4 addresses, register, 5 cycles, multiplexer 6, voltage source 7, resistor 85 control unit 9, Start and Reset keys 10 and 11, the control time register 12, the outputs of the address register 4 are connected to the information inputs of the multiplexer 6 and the decoder 3, the outputs of the latter are connected to the first inputs of the corresponding blocks 2.1 - 2.P of the signal checks, the remaining seven inputs of which are connected respectively - on with five outputs of control block 9, ne the output of the voltage source 7 and the first output of the resistor 8, the second one, the output of which is connected to the second output of the voltage source 7, the outputs of the register of 5 cycles are connected to the address inputs of the type-6 of the first, the seventh input of the control unit 9 connected respectively with the first output of the resistor 85 outputs of the overflow of registers 4 and 5 of the address and cycles, outputs of the multiplexer 6 and keys 10 and 1i Start and Reset, the sixth and eighth outputs of the control block 9 are connected respectively to the counting input of the address 4 and quenching inputs register 4 and 5 addresses and cycles, the outputs of blocks 2.1-2:, and the formation of test signals are connected to the corresponding contacts of the checked product 13; the counting input to the blanking input of the control time register 12 is connected respectively to the overflow taps and the input of the hash} and regisr 4 addresses, the output of the full register of time 12 to co-troll with - ;; tinin

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with

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with the third input of the control block 9 and the counting input of the register 5 cyclops,

Each block 2.1 - 2.p of the formation of verification signals contains a register of 13 states, a decoder of 14 states, ele: eite OR 15, element 16, elements 17 and 18 of which setting and indicator 19, the first and second codes The state register 13 is connected to the inputs of the state decoder 14, the second and third outputs of which are connected to the control inputs of the corresponding elements 1 and 18 of the switch. and, the test voltage inputs of which are connected to the sedans-a1m and the eighth inputs of blocks 2.1 - 2.P forming audit checkers, the codes of the switching elements 17 and 18 are connected to the outputs of blocks 2.1-2.P formed:; checks, information inputs of the state register 13 are connected to the second and third inputs of the 2.1 2P blocks of the formation of the verification signals and the output of the PUI i ISj element, the inputs of a coherent connection respectively to the OUT of the third bit of the state register 13 and the fourth input of the 2 1 - 2.P forming test signals, input Synchronization of the state register 13 is connected to the output of Mi2HTa and 15, the input; - 1 of which is connected respectively to the fourth inverse output of the state decoder 14 and nepiibLM and the fifth inputs of the blocks 2.1 -. The input of indicator 19 is connected to the output of the third state of the register of state 13, the quenching input of which is connected to the sixth input of blocks 2, 1 - 2 "M forming the signal of the signal; pk1:.

The device also contains tires 20 - 24,

Control block 9 (Fig. 2) has a register of 25 coded states, block 26 of output functions; block 27 of functions; excitement 5 driver 28, address register 29, control time register 30, cycle register 31, trigger trigger 32 and delay elements 33 36, with seven inputs of control unit 9 connected respectively to input of a wireless controller 28. inputs registers 29 - 31 a / ipeca, control time, cycles and flip-flop 32 signals with the fifth and sixth inputs faded 26 EY- functions, the first eight outputs

Afterwards, respectively, are connected to eight outputs of control unit 9, four codes of register 25 of coded states are connected, respectively, with the first four inputs of block 26 of output functions and block 27 of excitation functions, the outputs of the latter are connected respectively with four inputs of register 25 of coded cocToHHi ij R - the input of which is connected to the tenth output of the block 26 of output functions, the ninth output of which is connected to the input of the delay element 33, the output of which is connected to the C input of the register of 25 coded states and to the input of the element nta 34 delay, the output of which is connected to the seventh input of the block 26 output functions and the input 35 of the delay, the code of which is connected to the eighth input of the block 26 output functions R-inputs of registers 29-31 address control time; cycles and trigger 32 of the start signal and the input of the delay element 36, the output of which is connected to the ninth input of the block 26 of the code functions 5 and the ninth inputs of the block 27 of the functional excitation connected to the outputs of the former 28, registers 29-31 of the address, control time, cycles and trigger 32 signal Start.

Blocks 2.1-2.P of forming a test signal are used to excite the contacts of the tested product 1 by generating different polarity from the outputs of the voltage source 7 for indicating the contacts of the circuits with defective insulation and for blocking the excitation of the contacts in the circuit with defective insulated against reclosing.

The operation of the forg-shrov units of the verification signals is determined by the codes set in state register 13, the following codes are distinguished in state register 3:

, 00 - neutral state j

.01 - excitation of the corresponding contact of the tested product 1 by the first pole of the voltage source 7;

IO - excitation of the appropriate ;; tact of the tested product 1 with the second pole of the source 7 voltage;

.11 - blocking the wind; denig; corresponding contact of the tested product 1;

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one. . - the indication corresponds to the contact checked 1, if the contact belongs to a circuit with defective insulation.

The contacts of the tested product 1 are excited by the voltage at the outputs of the switching elements 17 and 18, to the control inputs of which the signals from the second and third outputs of the state decoder 14 are fed. The fourth inverse, the output of the state decoder 14 is the lockout output of setting the codes on the state register 13. The blocking is performed by prohibiting the excitation of the AND element 16, which generates the synchronization signal of the state register 13. The third bit of the state register 13 is used to turn on the indicator 19 and to block the blanking of this bit, the latter is done by connecting the output of the third bit of the state register 13 to the input of the I element of LTM 15 whose output is connected to the third; register 13 states.

The decoder 3 serves to select the block 2.1 to generate a verification signal when the corresponding code is set in the state register 13 of this block.

Address address register 4 is used to set the address code of blocks 2.1-2.P to generate test signals and to determine the polarity of the excitation voltage of the contacts of the tested product 1 from the outputs of the voltage source 7 in this test cycle.

A register of 5 cycles is necessary for determining the codes of testing cycles, in which the contacts of the test product 1 are divided into two groups, excited by different poles of the voltage source 7.

Multiplexer 6 is used to implement the signals used to break the contacts of the scanned

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divide 1 into groups.

The frequency of the signals at the output of multiplexer 6 is equal to the switching frequency gc; register register 4 addresses selected by the code set in the 5 cycles register.

Voltage source 7 serves to generate the voltage required

for insulation testing verifiable. products 1.

Resistor 8 is necessary for fixing the circuits with defective insulating yu, which is carried out by means of a propeller / ram and a voltage drop across this terminal.

The control unit 9 is designed to generate control time-distributed signals necessary for operation of the device in various.

Keys 10 and 11 Start and Reset are used to generate Start and Quench signals, which are used to start up the device for checking the insulation in the tested product 1 and gash1} and register elements when the device stops.

Register 12 of the control time generates an interval of 1 time; necessary to measure the isolation of the circuits of the tested product 1 in this test cycle.

Register 25 of coding states (FIG. 2) is intended to store operation codes for the device to perform operation when checking the insulation of the circuits in the product being tested.

The output functions block 26 generates command signals, which are fed to the individual units of the device, when performing the control operation of the insulation in the circuits of the tested product 1.

Shaper 28 and triggers triggers 29-31 and flip-flop 32 serve to convert the st-voltage drop across the resistor 8 of the overflow signals of the registers 4, 5 and 12 of the address, ng and 7:; control straps into logical signals, used: Use: in block 27, the function function is: dede, 3j; e ™; the delayed cops 33 36 are required to generate the switching signals of the register 25 of the coded states of the 13 and 4 5 switching registers to the 12 state, address, cycles and monitoring time,

The table shows the functions. the state of the device when checking and: -e (ISOLATION of a computer in the product; :: -: 1 „

Variable value and funkt; s in the table;

X1 - signal from Bshod resistor 8 :; X2 - register overflow signal; 4 addresses;

X3 is a signal of quail: not register 12 times cntr- and; |

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X | - signal re; psh and regist5 cycles;

X5 - signal at the output of the multiplexer 6 |

Hb - the signal at the output of the key 10

X7 - key output signal 11 Reset

Z1, Z25 Z3, Z4 - register bits of 25 coded states;

U1 is the signal for setting the first bit of register 13 of state j

Y2 is the signal for setting a second bit of state register 13;

UZ - the signal of installation of the third bit of the register of the 13th state;

Y4 is the executive signal for setting codes in state register 13; A5 is a state register quench 13;

Y6 signal change codes in address 4;

V7 of the damping signal of the register 4 addresses and the register 12 of the monitoring time;

V8 is a register blanking signal of 5 cycles;

Y9 - s} 1 excitation signal of the delay element 33;

alj a2, i3 and a4 are the output signals of the block 27 of the functions of the excitation; vdi, posad, ayupJ; and the setting values of the corresponding bits in the register of 25 coded states.

Analytical expression of the function block 26 output functions taaog

F1 Y1 Mv (Z3 V 21Z4) V / Z1Z4;

F2 Y2 M from VJ1 Z4) V Z 1 Z4;

F3 Y3 Z1Z4 V Z1Z4;

F4 Y4 Y4 Z2C2;

F5 Y5 X6U X7;

F6 Y6 - Z3C3;

F7 - Y7 ZiZ3Z4C3;

F8 UB Y5

F9 - Y9 (Z1 V Z2 VZ3) C4 V X6-;

F10 Y8 - Y5 |

rd-a M:, - a signal from the code of the line p lekksra b;

g i g / g 4 V; .. i 5 ъ J 3

C4 - e: Igals from the codes of the elements j3; 6 co-OTBeTCTBeiiHO

Personalities:) 1, GhOTcn 27 functions of excitation 1: 1;; г1 ,, | уюи; ю View:

a1 Z1Z2Z3Z4X1 V

a2 ZIX1 V X6 V Z2Z3X2 VZ2Z3X1X3X4 V Z1Z2-N / Z2Z4X1X2 V ZIX; AZ X6V Z2Z3 V Z1Z3X1X4 VZ2Z4X1 V X1Z2Z4V Z1Z2Z4; a4 Z1Z2Z3 V X1Z4.

In this case, X1, X2, X3, X4, X6 are converted on the elements 28, 29, 30, 31 and 32 input variables of the control unit 9.

The device may be in the following states:

- state 1 - initial (non-working);

- state 2 - switching on switching element 17 or 18 (setting codes .01 or, 10 in the register

13 depending on the value of the signal at the output of the multiplexer 6);

- state 3 - control (isolation test in the circuit of item 1 by the voltage drop across the resistor 8);

-state 4 - extinguishing of the register 4 addresses in case of detection of insulation defects in the chains of item 1

(Xi 1);

- state 5 - disconnecting the contacts of the circuits of the product 1 by setting the codes .00 in the register 13, defined by a code on the address register 4;

- state 6 - code change - on the 4 addresses register;

 state 7 - switching on the contact of the circuit of the product 1 under the voltage of the voltage source 7, if X1 O (the first circuit with the defect is detected), the inclusion of the third bit in the register 13;

- state 8 - code change in the register of 4 addresses;

- state 9 - disconnection of the contact of the product 1 in order to search for the second circuit of the product 1 with a defective insulation;

 state 10 - blocking register 13 (setting code 1 Г1 in register 13) when a second defective circuit of product 1 is detected, impingement of the third digit in register 13,

The device is put into operation by pressing the 10 Start key (Xb 1), and the device switches to state 2 (set 2 of the table

In state 2, a second connection is made, determined by changing the codes on the address register 4, the contacts of the circuits of the product 1 under the voltage of the voltage source 7, and the polarity is determined by the signal value at the output of the multiplexer 6.

Signal X2 1 transitions to state 3 (state of control), in which extracts are made under the voltage of the contacts of product 1. Depending on the value of the signals X1, X3, X4, the device from

3 enters state 2 (X 1, set 7), state 1 (X4 1, set 8) and state 4 (XI 1, set 9). In the first case (X1 1), a code change is made.

in the register of 5 cycles and the connection of the contacts of the circuits of the product 1 under the voltage of the source 7 of the voltage is made. In the second case (X4 1), the device returns to its original state, since the device operates to check the insulation of the chains of the product 1, and in the third case (X1 1), there are defects in the insulation of the chains of the product 1. In state 4

The register 4 addresses and the monitoring time register 12 are quenched and the device enters state 5. In state 5, the contact of the circuit defined by the code on address register 4 is disconnected, i-. divided 1 from source voltage 7. Depending on the value of signal XI, the device changes from 5 to 6 (X1 1) or to

state 7 (XI 0).

In state 6, the code in register 4 of address and is changed. the device enters the state

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IN SOSTOYAN1SH 7, the defective circuit contact is connected to the voltage of the voltage source 7 and the third discharge register is set to the third state in the unit state to indicate the contact of the negative defective circuit of product 1, the device goes to state 8,

In state 8, the address code is changed in address register 4 and transition to state 9.

In state 9, it is made from: connecting the contact of the circuit defined by the code on the address register 4 from the voltage source 7 and transfer to

This is 8 (X 1 i) or n n comp. 10 (X1 0),

In state 10, the code 111 is set to the state register 3, register 4 is cleared by address i; the register 12 of the control time and the transition of the state to the state In state 10, the blocks are displaced, the recording of the information in the register 13 and the activation of the indicator 19

When the key 11 is pressed. The reset is performed to extinguish the register of the device elements and to return to the initial state (dial 19 of the table).

Thus, reducing the time spent on determining defective circuits is achieved by introducing third bits of the - D registers to form validation signals, which allows the defective circuits to be determined without loss of time for printing the results, as well as by introducing a control time register j that allows you to save the holding time under voltage in case of a defective circuit.

Claims (1)

Invention Formula A device for monitoring a) containing blocks for forcing the test signals, a decoder 5 address register, cycle register, multimeter voltage source, resistor ;, control unit, Start and Reset keys. the outputs of the address register are connected to the information inputs of the NryHbTi-irmeK-a and the decoder, the outputs are gradually connected to the first inputs of the corresponding blocks of forkyrozapi check signals and the remaining csr-sb inputs of which are connected respectively to the first, second, third, fourth and p The first outputs of the control unit, with the first output of the voltage source and the first height of the resistor, the second output of which is connected to the second voltage source, the codes of the register of cycles are connected to the address inputs of the multigatecor; The second, fifth, fifth, sixth, and seventh inputs of the control block connect the corresponding BGHfio with the first output of the resistor, the output of the address registers and cycles overflow, the output of the optical selector and the Start and Reset keys, the seven, eighth and eighth outputs of the control block are connected ggeino with a counting input of the register of address m from the output of the –shaft reg reg of the ijoTs addresses of n cycles, the outputs of the test signal generating units are connected to the corresponding contacts of the tested product, each The test signal generating unit contains a status register, a state decoder, element Pi, a switching circuit, the first and second outputs of the register are copied. connect} w) s, g: am p-1 1 of the amplifier is ngsh, the second and third outputs of which are connected to the control inputs of the corresponding gsmutation elements, arei xi; tatel: gogo voltage of which is connected to gray, and the eighth block inputs; -: 3 npoBeriKH signal generation. fumes; switching elements Sed; inv - l with the outputs of the block forming the signal lOB check., that is, with the reduction. time Fra search for defective items in it, a time control register has been entered into it; The input and output of which are connected with: It is connected with the overflow code and the address register input input, the output of the control time register is connected to one third; m code, control unit and center: M terminal input is 1 pstr shch.chov, za;}, ü; th block of forming signals n 1 checking, enter the third digit of the state of the indicator and the element OR, and; The n-register registers are connected to the second and third inputs of the Block formag.Anp signal of the check and the output of the element j Ilf, the inputs of which are connected according to the output of the third bit of reg; −gr ra; 1 and the fourth input of osioi: a L reinforce the check signals; and the input of the register register state is soy.cip with the output of the AND element, whose inputs; oedl; It corresponds to the fourth inverse of de (ifuretor state. h gharva -. ii p - block inputs are formed.; skg ggals jipoBepKii; indicator input is connected to the output of the third bit of the state, input raiueHisH of which connect with iiiacTbiK block injection of the formation of a Cy1 ialosis n-onei) Kii. u I lU about e X I about g one l m "9 GM ai . (-, Oj TS "H (a sc kjs 0) Z nк oo oh tCf about . . chg N fS N Oi oi yoo o Ik i I Io Is Is & cS ai "a II uk oo uгt. a 7 7 7 7 t at I t t f G t t 7 t 7 t - - hch h «cht1P | (. , ooooooooooooooo "" - "ooo o - - -" - "ooo ooo" ooo - o - About - -oo-oo-o-o-o- o “- - OOO oooo o o -. OO- - - - - - - - - - - oooooeooooooooo-ooo o oo.ooooaoo "-ooooooe9. 00 m. - LLC GS -Ltd. V ОООООООООООООООООООOO - o o "-" - - o oor - o "-" -o-o - -. oooooh “oh .-  . . . . .o oi oo - . "About" About "All" - " OOOOOOOOOOOOOOO --- “- -.  - o.o -oo "-eoo- eeo - -" -oooooo - - OOOOOOOOOOO - O.- OO h . , LTD., LTD. .about. ooooooooooooo LTD . -. . " ooooooo - ooooooooooo. OOOOOO - - LTD. ohh oh -, - “ooooooooooo oo d.  - “MF i4 r5cn“ n. I A It About Us Well -o - “h“ tfi “JS w win chgl 2 J 12 Fi2.2.