SU1434546A1 - Code inverter - Google Patents

Abstract

The invention relates to a pulse technique, telecommunication, and can be used to transform a code by generating insertion pulses. The invention allows to increase the speed and simplify the converter. The code converter contains the 1 shift register, the OR 2 element, 3 unit potential potentials, and the zero potential bus 4. 2 Il.

Description

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ABOUT)

I The invention relates to a pulse-hojft technique and telecommunications and can be used to form an insert-insert into information transmission systems.

The purpose of the invention is to increase the speed and simplify the code converter.

Figure 1 shows the functional diagram of the code converter; 2, timing diagrams for his work.

I The code converter contains a 1-shift register, an element OR 2, a tire 3 of a single potential, and a bus 4 of zero {ω potential.

When used as a rHJcTpa 1 shift of a chip with open collectors, the element OR 2 can: be completed according to the installation scheme Hcje OR.

; The code converter works as follows.

I At the clock input of the shift register 1 clock signals are received (4ig.2a). Information pulses of a dyuichny code arrive at the serial information input of register 1 (Fig. 26). On register codes 4 1, sequences of ig pulses are formed, shifted one arc dhg relative to each other (fig. 2d-2d). As a result of the summation of these sequences on the element -OR 2 forms m1, logical O pulses are corresponding to the position of the fourth O input sequence (Fig. 2e).

A logical pulse O, which enters the recording mode control input - shift, switches the register

1 to the information recording mode, while the next operation cycle of the converter on the parallel information input of the first bit is written logical 1 (insert pulse), and on the inputs of the remaining bits - logical O. Logic 1 from the output of the element OR 2 translates Register 1 in the forward shift and in the next cycle of operation of the information converter recorded in the previous cycle will begin to advance to the output of register 1 (Fig. 2g).

15 As the shift register 1, the high-speed register 100 IL 141 can be used.

20

Claims (1)

Invention Formula A code converter containing a register, the serial information input of which is the information input of the converter, the outputs of all bits of the register, except the output of the last bit, are connected to the same inputs of the OR element, the output of which is connected to the control input of the register, the bus of a single potential and a zero potential bus, characterized in that, in order to increase speed and simplify the converter, a parallel information input of the first register bit is connected to the unit bus potential, the parallel information inputs of the remaining register bits are combined and connected to the zero potential bus, clock . „Last bit input and output re- 40 the gist are b clock input and the output of the converter. 35 Invention Formula