SU1317675A1 - Binary code-to-three-position code converter - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to simplify the converter and increase its noise immunity. The converter contains a source of 1 binary information, a successive register 2, a synchronization unit 3, an inverter 4, a pulse shaper 5, a parallel register 6 consisting of triggers 7.8 and 9, an encoder of 10 characters consisting of AND-NOT 11 elements -16 and RShI 17 and 18 cells, a code signal generator 19, consisting of flip-flops 20, 21 and 22, a relative mono-pulse signal generator 23, consisting of I-NE 24-29, triggers 30-31 and integrating circuits 32. and 33. This embodiment of the converter eliminates it from the composition of the field analyzer Balancer and multiplexer, which simplifies the converter. Improving noise immunity is achieved by increasing the duration of the linear signal pulses using the input shaper 23. The transducer is characterized by the performance of shaper 19. 2 Cp f-ly, 3 ill. S (L 2: with O5 cl

Description

The invention relates to telecommunications and can be used in digital transmission systems with various transmission media.

The aim of the invention is to transform the converter by eliminating the polarity analyzer, the balancing unit and the multiplexer and increasing the noise immunity by increasing

triggers 30 and 31 and integrating circuits 32 and 33.

Converter binary code in the three-position code works as follows.

The binary information (Fig. 2a) of the source 1 is fed to the input of the sequential register 2, to the synchronization input of which the pulse duration of the linear signal from the synchronization unit 3 of the signal is fed (Fig. 26) through the inverter 4. Thanks

the shift of the binary information by the clock signal at the outputs of the successive register 2 simultaneously there are three bits of binary information (figv, d, e).

When divided by three binary signals, this is the first

Fig. 1 shows a structured electrical circuit for converting a binary code into a three position code; Figures 2 and 3 are time diagrams that explain his work.

The binary-to-three-position code converter contains the source of 1 binary information,

ny register 2, synchronization unit 3, 20 output of shaper 19, code inverter 4, shaper-signal shaper 5, code signal is generated, parallel register 6, which includes triggers 7-9, 10 character encoder, which includes elements I-NE 11 716 and elements OR 17 and 18, shaper 19 of the code signal, which includes triggers 20 ™ 22, for25

(Fig. 2e), at the instants of occurrence of the pulse fronts of which, in parallel register 6, sequentially records binary information at every three adjacent clock intervals.

The purpose of the 10-character encoder is to convert binary information into ternary information according to the code table:

the globalist 23 relative monopulse signal, which includes elements of AND-NOT

For this, information about the characters in the first, second and third bits of each binary group from the inverse outputs of the trigger 7,8 and 9 and from the direct output of the trigger 7 goes to the corresponding inputs of the 10-character encoder (FIG. 2, g, g, and, to).

To register a binary group 100, the inputs of the NAND 11 element are connected to the inverse outputs of the flip-flops 7 and 8 and to the direct output of the flip-flop 9. With the occurrence of 1 simultaneously on the indicated outputs (shaded areas in FIG. 2, 3, and 2) The output element AND-NOT 11 is formed O (Fig.2l). The binary group 000 is registered by connecting the inputs of the NAND element 12, respectively, to the inverse inputs, the outputs of the trigglers 30 and 31 and the integrating circuits 32 and 33.

Converter binary code in the three-position code works as follows.

The binary information (Fig. 2a) of the source 1 is fed to the input of the sequential register 2, to the synchronization input of which the binary shift information of the clock is supplied. the signal at the outputs of the serial register 2 simultaneously contains three bits of binary information (Fig. 2c, d, e).

When divided into three binary clock signal (Fig. 26) on the first

the output of the shaper 19 of the code signal is formed the code signal

the output of the shaper 19 of the code signal is formed the code signal

(Fig. 2e), at the time of occurrence of the pulse fronts of which, in the parallel register 6, binary information is alternately recorded at every three adjacent clock intervals.

The purpose of the 10-character encoder is to convert binary information into ternary information according to the code table:

4U of 7-9, With the simultaneous occurrence of 1 at the indicated outlets (shaded areas in fig.2j, h, k), at the output of the element AND-NO 12 forms O (fig.2m).

10 characters of the second and first bits of the ternary characters are read in the encoder by two periodic sequences.

Q pulses from the outputs of the driver 5 pulses.

The ternary units of the first bits (Fig. 2p) appear at the output of the AND-NE 13 element with 1. inverse output 55 during trigger 7 (Fig. 2g) and the AND-NO 12 element (f. D.2m) at the instants of appearance. read pulses (Figure 2o). Ternary units of the second discharge (fig.2p at the output of the element AND-NO 14 are possible,

if at the instants of the appearance of pulses (fig. 2n) in state 1 there are outputs of flip-flop 9 (fig.2i) and an AND-HI element 11 (fig. 2l). The pulses corresponding to the ternary units of the first and second bits (fig.2p, p) are summed in the element OR 17 (fig, 2c) and arrive at the first output of the encoder 10 characters.

Ternary twos of the first discharge appear in the form of short pulses (fig, 2t) at the output of the element NE-15, if the reading pulses (fig, 2o) coincide with 1 at the inverse outputs of trigger 8 (fig, 2h) and the element I- NOT 11 (fig, 2l). When reading ternary twos of the second bit, the sequence pulses (FIG. 2n) of the driver 5 pulses appear at the output of the AND-HI element 16 (FIG. 2p) with 1 at the inverse of the output of the trigger 9 (FIG. 2k) and at the output of the And- NOT 12 (fig. 2m); Through the element OR 18, the pulses (fig, 2f) characterizing the ternary two of both bits (fig, 2t, y) are fed to the second output of the encoder 10 characters,

As a result of the appearance of 10 symbols of pulses at the output of the encoder (FIG. 2c, f) of ternary units and twos (the absence of pulses of ternary ones and twos corresponding to threefold zero, binary information is converted at every three clock intervals (FIG. 2a) to ternary information on two clock intervals in accordance with the earlier conversion table of symbols; code ЗВ2Т,

In accordance with the method of generating relative multi-position signals, the transmission of three ternary symbols is carried out as follows.

The transmission of the first ternary zeros occurs without changing the modulated parameters. Therefore, these symbols are not represented in the encoder 10 symbols, and on the corresponding cycles (G and 3) in the output relative mono-pulse signal (.x2x) any voltage level of the previous clock interval is saved.

When transmitting the second ternary symbol 1 when a short pulse appears at the output of the element OR 17 (FIG. 2c), the output voltage should

fO

J5

3176754

increase by ulJ or decrease by 2 liters and.

When transmitting the third ternary symbol 2 and, accordingly, when a short pulse appears at the output of the element OR 18 (FIG. 2f), the output voltage should increase by 2 D and either decrease by e U. Moreover, in the case of any sequence of ternary symbols, the three-position relative monopulse signal should not exceed 2uU (Fig. 2x), i.e. The signal should be three-level. According to this algorithm, a high voltage level at the output of the converter is set (FIG. 2x), if of the two triggers 30 and 31 of the former 23, only the trigger 30 is in state 1. The average level is set, if the triggers 30 and 31 are in the zero state, and low - at 1 at the output of trigger 31 only,

20

Let a high voltage level be observed at the output of the converter at the clock interval A (fig, 2x), then when a pulse appears at the output of the element OR 17 (fig, 2c), it can enter the output of only the AND-NOT element 24, since. at this moment, 1 input from the direct output of trigger 30 is supplied to its input. This pulse is fed to the input of the installation O of the trigger 30 and to the input of the installation 1 of the trigger 31, which leads to the formation of a low output voltage level on the clock interval B,

to a voltage change of 2uU. If on the next: step B (FIG, 2x), a triple unit will also be transmitted, then due to 1 at the direct output of the trigger 31 a pulse

it may appear at the output of only the AND-NE element 26 and it will trigger the trigger 31 to the zero state. But trigger 30 continues to be in the same state. Therefore,

the time interval B is set to an average level, and the voltage variation is plus l11. The appearance of a pulse in the same circuit of the second ternary symbol 1 with an average level

on the tact interval 3 coincides already with 1 on the inverse outputs, triggers 30 and 31, Therefore, having passed through the element AND-NOT 25, a short pulse will translate trigger 30 into a single

ten

51317675 state and will set a high level of the output voltage at the next cycle I. In comparison with the previous cycle 3 (fig.2x), the voltage will change by the value + li.

If the clock interval D at the output of the element OR 18 turns on a pulse (fig.2f), then due to 1 on the inversion of the outputs of the triggers 30 and 31 it can appear at the output of the element IS NOT 28. This pulse will switch the trigger 31 in a single state and on the clock interval D a low output voltage level is set.

Compared to tact G, the change in voltage will be -uU. The appearance of a pulse at the output of the element OR 18, which at the next cycle E coincides with 1 at the direct output of trigger 31 and, respectively, at the second input of the element IS-HE 29, passed through which the pulse switches trigger 30 to one and resets the trigger 31, which will lead to a high level of output voltage at the clock interval E and, compared to the previous clock cycle, the voltage change will be + -2ill. The next imtroichnye symbols in two bits from the encoder of 10 symbols requires a code signal, the period of which must be equal to the repetition period of ternary groups - 3Ti The code signal is generated in the shaper 19 of the code signal.

During the period of the code signal, the status of the trigger 20,21 and 22, the driver 19 of the code signal is changed in the following sequence. The unit state of the trigger 20 (Fig. 3b) at the time of the clock edge (Fig. 3a) of the synchronization unit 3 with a delay of T changes to a single state (Fig. 3g) of the trigger 21. With an additional delay per T / 2 front the clock signal (Fig. 36) of the inverter 4 transfers the flip-flop 22 to the state 1 on the direct output (Fig. D). Due to the feedback from the inverse output of the trigger 22 to R - the input of the trigger 20, its output voltage is reset (Fig. ≪ Desc / Clms Page number 2) to the zero state. At the interval T / 2, this state is transmitted by the next edge of the clock signal (Fig. 3a) to the output (fig. D) of the trigger 21. Next, after time

15

20

pulse (Fig. 2f) at a clock interval of -30 T / 2 clock signal (Fig. 36) is at a time when 1 is on the forward output state is transferred to the trigger 30, connected to the input output (fig. D) and sets the And element -NE 27, passed through them, the unit state on the inverse pulse will reset trigger 30 and due to the zero state of triggers 30 and 31 on the clock interval G will be set

the output (FIG. Ze) of the trigger 22 and, consequently, to the R — input of the trigger 20 (FIG. Ze), which restores the possibility of its switching by a signal arriving at the C — input. Therefore, with another delay on

medium voltage level. By comparison, with tact E, the change in voltage will be -uU.

Due to the feedback from the outputs of the flip-flops 30 and 31, the changes of states at the inputs of the elements AND-NOT of the former 23 should be observed after the termination of the pulses of ternary units (Fig. 2c) and twos (Fig. 2f). To ensure this condition between the outputs of the flip-flops 30 and 31 and the inputs of the AND-NOT elements 24-29, the integrating chains 32 and 33 are introduced.

Thus, by means of a generator 23, the method of generating a multi-position signal is realized, and for a particular variant, a three-level relative monopulse signal is generated.

To write binary information on three clock cycles and a parallel register 6 and then read

of ternary symbols in two bits from the encoder of 10 symbols a code signal is necessary, the period of which must be equal to the repetition period of ternary groups - 3Ti The code signal is generated in the shaper 19 of the code signal.

During the period of the code signal, the status of the trigger 20,21 and 22, the driver 19 of the code signal is changed in the following sequence. The unit state of the trigger 20 (Fig. 3b) at the time of the clock edge (Fig. 3a) of the synchronization unit 3 with a delay of T changes to a single state (Fig. 3g) of the trigger 21. With an additional delay per T / 2 front the clock signal (Fig. 36) of the inverter 4 transfers the flip-flop 22 to the state 1 on the direct output (Fig. D). Due to the feedback from the inverse output of the trigger 22 to R - the input of the trigger 20, its output voltage is reset (Fig. ≪ Desc / Clms Page number 2) to the zero state. At the interval T / 2, this state is transmitted by the next edge of the clock signal (Fig. 3a) to the output (fig. D) of the trigger 21. Next, after time

five

0

0 T / 2 clock signal (Fig. 36) nous unit state on inverse

the output (FIG. Ze) of the trigger 22 and, consequently, to the R — input of the trigger 20 (FIG. Ze), which restores the possibility of its switching by a signal arriving at the C — input. Therefore, with another delay on

40 1/2 clock edge (Fig. 3a), trigger 20 switches to state 1 (Fig. 3b) and this completes the formation of the period of the code signal, the cycle of operation of the world 19 code signal. I

During each period of the code signal, the front of the signal (fig.Zg) from the output of the trigger 21 (the first output

The Q signal generator 19 is used (FIG. 2e) to write three bits of the binary number of a parallel register 6. After writing, reading (FIG. 2N) of the bits and then from delay to TT / 2 occurs (FIG. ) - the first bits in the encoder are 10 characters, respectively, with periodic sequences of pulses (Fig. 3, g).

7

which are created in the pulse shaper 5 using signals from the second and third outputs of the shaper 19 of the code signal from the outputs of the flip-flops 20 and 22.

Thus, the reading of ternary characters is carried out after writing binary numbers to parallel register 6, and the time between reading the neighboring ternary bits and the mini-1 pulse duration in the output signal is 3/2, 1.5 times longer than the clock interval duration. binary information.

Claims (3)

Invention Formula . 1. A binary code converter into a three-position code containing serially connected source of binary information and a serial register, the outputs of which are connected to the inputs of the corresponding triggers of the parallel register, C -. the inputs of which are combined, and the inverse outputs and the direct output of the last trigger are connected to the corresponding inputs of the symbol coder, as well as a synchronization unit, characterized in that, to simplify the converter by eliminating the polarity analyzer, the balancing unit and the multiplexer, an inverter is introduced, the driver of the code signal and the driver of the pulses, while the output of the clock pulses of the synchronization unit is connected to the input of the synchronization of the driver of the kodo eight O five 0 signal directly, and to. The synchronization input of the serial register and the other input of the code generator through the inverter, the code generator output of the code signal connected to the read input of the parallel register, and the other two outputs through the pulse shaper connected to the write inputs of the encoder. 2. The converter according to claim. 1, and t is characterized in that, in order to improve the noise immunity by 5 of increasing the duration of the linear signal pulses, the relative mono-impulse signal shaper was inputted, with the first and second outputs of the character encoder connected 0 to the corresponding inputs of the relative mono-impulse signal generator. 3. The Converter in PP. 1 and 2, characterized in that the shaper of the code signal comprises serially connected first, second and third flip-flops, the inverse output of the third flip-flop being connected to the R - input of the first flip-flop, C - the inputs of the first and second triggers are combined and are the synchronization input, C - the input of the third trigger is the input, and the output of the second trigger is the output of the code The 5 signals and the outputs of the first and third triggers are, respectively, the outputs of the recording signal of the driver, code-driver. th signal. Editor K. Voloshchuk Fi2.3 Compiled by V. Evdokimova Tehred V. Kadar Proofreader c. But ha Order 2437/56 Circulation 638. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4