RU1791960C - Device for digital information decoding - Google Patents

Abstract

The invention relates to instrumentation and can be used in equipment for magnetic recording of digital information. The purpose of the invention is to simplify the device for decoding digital information presented in the form of RLL code 2, 7, the device contains an input six-bit register 1, a frequency divider 2, elements 3-6, an inverter 7, elements OR 8, 9 and an output two-bit register 10, Simplification is achieved by combining the functions of code conversion and counting control of a group length counter. 2 ill. .

Description

F ig. 7

The invention relates to the field of instrumentation and can be used in devices for reproducing digital information from mobile magnetic carriers, presented in the form of an RLL code.

A device for decoding digital information; encoded according to the following rule:

 V th

NRZ: RUL2.7.,

11 Qfbo

101000

011000100

010001000

000100100

001100100100

001000001000

Such a device comprises an input shift register, group length determination logic, a group length counter, a code converter, a data register, and other elements 1.

The device is complex in circuit design and code conversion algorithm.

The closest in technical essence to the proposed one is a digital information decoding device containing a 6-bit input shift register with a pulse sequence input in the form of an RLL 2.7 code, a synchronization input and b outputs, a frequency divider with an input connected to the synchronization input of the input shift register, and the output connected to the sync input of a 4-bit output register with 4 inputs and 4 outputs, one of which is the device output, code group length counter, control circuit a code group length detector and an RLL to NRZ 2 code conversion circuit.

Such a device is complex.

The aim of the invention is to simplify the device.

Figure 1 shows a block diagram of a device for decoding digital information. Figure 2 is a timing diagram illustrating its operation. Code A - NRZ, code B-RLL, identical to code A.

The device contains an input register 1, made in the form of a 6-bit shift register, a frequency divider 2, which are divided into 2 clock pulses CLK2F (signal h); four elements And 3-6, inverter 7, two elements OR 8 and 9 and the output register 10, made on two D-flip-flops 11 and 12.

The essence of the operation of the device for decoding is to extract code groups from the RLL code sequence

1000 and 0100, which are the core of converting the RLL code to NRZ (1000 is converted to 10 and 0100 to 11). The exception is the code group

100100, which although it contains the group 0100, but must be converted to 000. For these purposes, when a group 100100 is found in the code sequence, it is forbidden to convert the code 0100 to 11.

The allocation of code group 0100 is performed by AND element 4 (signal) by signal d of input register 1, and code group 1000 is performed by AND element 5 (signal k) by

the signals of this input register 1, The selection signals of these code groups through the element OR 8 are fed to the information input of the D-trigger 11 (signal t), which is on the leading edge of the signal h

is set to a single state, forming at the output of the decoding device (signal p) the first unit of code groups NRZ 10 or 11, the formation of the second unit of code

group NRZ 11, which is a sign of group 0100 RLL, is carried out by the signal f of the input register 1 in the single state of the D-flip-flop 11 using the AND element 3 (signal i).

The generation of a signal that prohibits the conversion of code 0100, which is part of code group 100100, is performed by element I b (signal i), inverter 7, element OR 9 (signal n) and D-trigger 12

(signal o) by the signal R by the And element 5 and the signal d and g of the input register 1.

The signal, which is a prohibition signal, is fed to the inverse input of AND element 4.

. The D-flip-flop 12, the inverter 7 and the element, OR 9 form a controlled flip-flop with a counting input, which is set to the initial state at the beginning of each RLL code group with signals d and k, which allows

generate the inhibit signal I using the And element 6. The conversion of the RLL to NRZ code groups enclosed between the dashed lines is shown in the time diagrams shown in Fig. 2.

The simplification of the proposed device is achieved by combining the functions of code conversion and controlling the count length of the group length counter.

Claims (1)

The claims A device for decoding digital information containing an input register, the information input of which is the information input of the device, the input synchronization input of the input register is combined with the input of the frequency divider and is the synchronization input of the device. The output of the frequency divider is connected to the synchronization input of the output register, the first output of which is is the output of the device, the first to the fourth AND elements, the outputs of the first and second AND elements are connected respectively to the first and second inputs of the first OR element, the output of which is connected to the first infromation input of the output register, the output of the third AND element is connected to the first input of the second second OR element, the output of which is connected to the second information input of the output register, an inverter, characterized in that, in order to simplify the device, the output of the first bit of the input register is connected to the inverse input of the third element And, the output of the third bit of the input register is connected to the direct input of the second element AND and the second input of the second element OR, the output of the fourth bit of the input register is connected to the direct input of the third element AND, the output of the fifth bit of the input register is connected to the first direct the input of the first element And, the second direct input of which is connected to the first output of the output register, the output of the sixth bit of the input register is connected to the first direct input of the fourth element And, the output of which is connected to the inverse input of the second element And, the second output of the output register is connected directly to the second direct input of the fourth AND element and, through the inverter, to the third input of the second OR element, the third input of the first element. OR connected to the output of the third element AND ..... I / o} about Y j | o o o o o g r 1QDO 000100 100100 Q010Q100 A b  TTLTinnjb G .. P P f P P --- L-.  rt | jT.-, , P I P rj, P P P J l-nLJTJ4JThjT - -n - {l JTL ni. GP n I gil. rl t 00