SU1432594A1 - Device for displaying information - Google Patents

Abstract

The invention relates to computing and automation and can be used in the construction of display devices with a television method of imaging. The purpose of the invention is to improve the accuracy of the device. The device contains with

Description

one

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Go to four 1.11 blocks - 4 RAM, 5 luminance code sensor, address writing devices on Y 6 and X 7 coordinates, television scanner 8, buffer memory block 9, display unit 10, first to fourth multipliers 11 - 14, the first 15 and second 19 pulse distributors, the first switch 16, the HE element 17, the adder 18, the second switch 20 with the corresponding connections. An increase in the accuracy of the display is achieved by separately recording the weighted codes of the brightness of the points in blocks 1-4 of the operational memory, so that there is no loss of information arising from the discretization of mathematical coordinates of the samples during the formation of the raster array. 4 il.

one

The invention relates to computing and automation and can be used in the construction of display devices with a television method of image formation.

The purpose of the invention is to improve the accuracy of the device.

FIG. 1 is a block diagram of the device; on fig 2 - block diagram of the second switch; ; and FIG. 3 is a block diagram of a second pulse distributor; in fig. 4 is a block diagram of a first pulse distributor.

The device contains the first If second 2, third 3 and fourth 4 RAM blocks, a luminance code sensor 5, shaper 6 and 7 of the recording address of the Y coordinate and X coordinates, respectively, a TV scanner 8, a buffer memory block 9, an indication block 10, the first 11, second 12, third 13 and fourth 14

intelligent dispensers, first dispenser 15

one

pulses, first switch 16,

element 17, adder 18, second pulse distributor 19, second switch 20, first 21, second 22, third 23 and quarter 24 adders, decoder 25, first 26 and second 27 blocks of controlled inverters, element 28, third 29 , the fourth 30, the fifth - 31 —I of the. 32 blocks controlled by the inverter (rgm), the first 33, the second 34, the third (i) and the fourth, 1.1 th 36 elements of the MChI, (Lorator 37, the controlled inert) G J8 ,

 roist): 1 rLoot is as follows.

The blocks 1-4 of the RAM have a matrix structure and are intended for storing the brightness codes of the image elements. The total number of cells in the memory block is equal to the number of pixels, and the number of bits stored in a separate cell is equal to the luminance code. A certain block of RAM contains a fourth of the cells required to store the entire image; The recording is carried out in one of the cells of memory blocks 1-4, the readout - at the same time from the group of cells of memory blocks. The address of the cell to be written is determined by the codes on the inputs of the write addresses of blocks 1–4 of the RAM, the address of the readings is determined by the codes on the inputs of the read addresses. The peculiarity of the RAM blocks 1-4 is that they accumulate information: before writing to the selected cell, the luminance code that arrives at the input of the RAM block is added to the code read from the selected cell. This eliminates the loss of the useful signal, since one sample of the useful signal can be distributed over four cells of different blocks of 1-4 memory.

The luminance code sensor 5 at the first output generates successively, one after the other, the luminance level codes for each sample of the input image, and at the second output, the start sweep of the recording, for example, radar probe pulses and radar clock pulses associated with code counts luminance.

The formers 6 and 7 of the address of the recording of the coordinates Y and X respectively form the codes of the address of the recording of the counts of the input image coming from the sensor of the brightness codes, as well as the correction codes numerically representing the offset of the exact position of the reference image of the input image relative to the points of the discrete television raster formed on the screen display unit.

The control input of the formers 6 and 7 receives the clock pulses of the radar and the pulses of the start of the write sweep. The first information input of the formers 6 and 7 receives the line angle code, and the second information input - the coordinates of the beginning of the line.

On the first output of the formers 6 and 7, the higher bits of the write address code are formed, on the second output, the low order of the address code, on the third, the correction codes.

The TV shaper 8 for the frame and line sync pulses and clock pulses arriving at its inputs generates

The telecorrection pulse generator 15 Y distributes the correction codes transmitted to its second information input to four outputs. The distribution is carried out by taking into account the location of the cells of 1-3 stable memory in the selected groups. The first switch 16 has

10 information inputs and four control inputs. In terms of the potential at the input of the control switch 16 produces the connection of certain inputs with the corresponding

15 m vygodami. For example, when the log is zero at the control input and the fourth informational input, the tator is connected to the same name of the switch 16, and for logical

20 units at the control input ne and the second information inputs are, respectively, with the third and vertices, and the third and fourth information inputs are

25 first and second exits 16.

The adder 18 produces a composite of the higher bits of the address code in dinate X with the lower bits.

The first and second output codes are scanned by 3Cf addresses along the same coordinate.

ki on the line and on the frame, and on the third control output - the signal to switch the write-read modes.

Register-type buffer memory block 9 converts incoming amplitude parallel codes into successively following groups of samples of the television image. The synchronization input of the buffer memory block receives clock pulses, and the control input receives the pulses of recording the parallel code arriving at the information inputs of the adder 18.

The display unit 10 is a television video monitor (BKV) and converts the luminance codes of the image elements arriving at its input in the line-frame mode to the brightness of the corresponding element of the image. The operation of the unit 10 is synchronized with the information reading process by means of lowercase, frame clock pulses from the inputs of the device.

The multipliers 11-14 multiply the codes received at their inputs. First distribute

The correction pulse puller 15 of the Y coordinate distributes the correction codes received at its second information input on four outputs. This distribution is carried out taking into account the location of the cells of the RAM units 1-3 in the selected group. The first switch 16 has four

information inputs and four outputs, as well as control input. Depending on the potential at the control input, the switch 16 connects certain inputs to the appropriate inputs. For example, with a logical zero at the control input, the first to fourth informational inputs of the switch are tied to the same outputs of the switch 16, and with logical

to the unit at the control input, the first and second information inputs are connected respectively to the third and fourth transgressors, and the third and fourth information inputs are connected to,

the first and second outputs of the switch 16.

The adder 18 produces the addition of the higher bits of the address code in the X coordinate with the lower bits of the code

five

0

g s on the ground, the inputs of the switch

The second valve distributor 19 of the X coordinate correction distributes the correction codes received at the information input to two outputs. This distribution is made taking into account the location of the cells of blocks 1-4 of the RAM in the selected group, which is determined by the code arriving at the control input of the distributor 19.

The second switch 20 distributes the codes of the address of the Y coordinate to the four outputs. The write address code goes to the third information, input of the second switch 20. 5 The first, second and fourth inputs of the first and second bits of the write address code are X coordinates and the low order bits of the write address code are Y coordinates. Using the second and fourth

20 counts

changing the order of allocation of the address of the record depending on the location of the cells of the RAM 1-4 in the selected group.

When writing to blocks 1–4 of the RAM, a line with a slope of 9, consisting of a set of equal samples, "codes of the brightness of samples of a sequence of

It determines which part of the luminance code in the countdown falls into each of the selected cells. The code that enters the video signal input of the individual block 1–4 of the RAM is determined by multiplying the luminance code B by one of the correction factors b) (l coordinates X and bi, bij + i coordinates Y in multipliers 11-14.

The values of the coefficients bx are fed to the inputs of the multipliers 11c of the distributor 19 correction codes of the coordinate X, and the coefficients ly, bc are fed to the inputs of the multipliers 11c of the outputs of the distributor 15 pulses. What exactly are the coefficients (bx

Of course, counting by counting is applied to the first inputs of multipliers 11-14, from the outputs of which are fed to the video signal inputs of the corresponding memory blocks 1-4. Simultaneously, from the second output of the sensor 5 of the luminance code, the first inputs of the formers 6 and 7 receive pulses of the start of the write sweep and clock pulses. From the first output of sensor 5, a certain number (for example, one) of clock pulses corresponds to each count from the first output of sensor 5.

According to the code of the angle of inclination of the line at the second inputs of the formers 6 and 7, for each sample, the formers 6 and 7 produce the position codes for the coordinates Y and X, respectively, which can be represented as Y + AY and X + LH, where Y and X are integers h-2o is determined by which position of the codes; & Y and dH - fractional parts. At the same time, the higher bits of the position code X and Y (whole parts) define a cell of memory blocks with such an address

15

or bx4; by or bijti (input n specific multiplier 11-14

in a selected square of 2x2 cells, it occupies a cell of the memory unit associated with this multiplier. For the operative block.

and the corresponding image element 25 occupies the lower left corner of the selected screen of block 10, and the lower bits of the position code of the incoming reference relative to the image element with the coordinates X, Y.

The part of the position code in the coordinates X and Yp is the address of the entry in the corresponding coordinates X and Y, with the first. the outputs of the drivers 6 and 7 are fed to the corresponding address inputs of the RAM blocks 1-4 and are used to address one cell in each block 1-4. At the same time, the address codes for the X coordinate are fed to the first address inputs of blocks 2 and 4 directly, and to the first address inputs of blocks 1 and 3 - through the adder 18, to the second input of which the low-order code of the address along the X coordinate arrives. addresses arrive at the fourth address inputs of blocks 1–4 through the second switch 20. A set of write address codes at the inputs of blocks 1–4 determines the choice of four cells (one of each block) with coordinates (X, Y), (X + 1 , Y), (X + 1, Y + 1), (X, Y + 1), surrounding the exact position of reference.

Fractional position codes

thirty

35

40

45

50

The multiplication of the luminance code B is made by the coefficients bj and, for a memory block whose cell occupies the upper right corner, is b and, and for a memory block whose cell occupies the lower right corner, and by. The values of the coefficients bj (and bx-m are determined by the position of the reference relative to the nodes of the coordinate grid DF. The closer the reference position to the cell, the greater the coefficient corresponding to this cell and the smaller the second coefficient defining the part of the luminance code that falls into the opposite cells of the selected square.

When the coordinates of the cell coincide with the coordinates of the reference (,), the entire luminance code enters this cell (since the corresponding coefficients for it are 1), and the luminance code is written to all other cells, equal to zero, since one or both of their coefficients are 0. In If only one reference coordinate coincides with the coordinate of the cells (for example, the X coordinate,), the luminance code B is distributed only to; between two cells (since

of reference LH, Y, determining offset 55 is one of the coefficients b or bx - (of reference relative to the position of the element is equal to zero, and the other to unity). These images with coordinates X, Y, the cells are located in the selected square from the outputs of the formers 6 and 7 on the distributors 19 and 15 of the pulse one above the other. The sum of all coefficients bx + b, + by + bijH 1, than

325946

It determines which part of the luminance code in the countdown falls into each of the selected cells. The code that enters the video signal input of a separate memory block 1-4 is determined by multiplying the luminance code B with one of the correction factors b. ,, b) (l coordinates X and bi, bij + i coordinates Y in multipliers 11-14 .

The values of the coefficients bx are fed to the inputs of the multipliers 1114 from the distributor 19 correction codes of the coordinate X, and the coefficients ly, bc + 4 are fed to the inputs of the multipliers 1114 from the outputs of the distributor 15 pulses. What exactly are the coefficients (bx

Yu

2o is determined by which position is 15

determined by which position

or bx4; by or bijti (fed to the inputs of a specific multiplier 11-14,

determined by which position

in a selected square of 2x2 cells, it occupies a memory location associated with this multiplier. For an operative block, a cell whose cell is

0

five

0

five

0

The multiplication of the luminance code B is made by the coefficients bj and, for a memory block whose cell occupies the upper right corner, is b and, and for a memory block whose cell occupies the lower right corner, and by. The values of the coefficients bj (and bx-m are determined by the position of the reference relative to the nodes of the coordinate grid DF. The closer the reference position is to the cell, the greater the coefficient corresponding to this cell and the smaller the second coefficient defining the part of the luminance code that falls into the opposite cells of the selected square .

When the coordinates of the cell coincide with the coordinates of the reference (,), the entire luminance code enters this cell (since the corresponding coefficients for it are 1), and the luminance code is written to all other cells, equal to zero, since one or both of their coefficients are 0. In If only one reference coordinate coincides with the coordinate of the cells (for example, the X coordinate,), the luminance code B is distributed only to; between two cells (since

one of the coefficients b or b x - (equal to zero, and the other to unity). These cells are located in the selected quad-

one above the other. The sum of all coefficients bx + b, + by + bijH 1, than

the total luminance of the four cells forming this sample is provided equal to the luminance of sample B from sensor 5, regardless of the offset from the coordinates of the cells. The sum of the coefficients bc and b is equal to one regardless of the value of the x coordinate.

The coefficients bc and b, have a similar distribution. The coefficient bx4i is numerically the offset code X along the X coordinate of the position of the input reference relative to the cell with the X coordinate, and the coefficient b is the offset code relative to the cell with the coordinate X + 1. Correspondingly, it represents the distance along the Y coordinate of the reference position relative to the cell with Y coordinate, and by relative to the cell with Y + 1 coefficients by + i and are equal to fiY and DH, respectively, a, lc 1-6X.

1 l of reference, located at an equal distance from each of the four surroundings of its cells, bj.bxf Y b, y, 5, and luminance codes of 0.25 V are sent to each cell for reference, the position of which coincides with the center of the display element on the ecra, and b, b (, a, b. Finally, for the reference, which occupies an intermediate position relative to the cells surrounding it, 0.25, and bx + by 0.75 and the luminance code falling into the upper right cell is approximately 0.56 V, in the upper left cell and the lower right cell - at 0.19 V, in the lower left cell 0.06 V. In this case, in separate cells memory blocks luminance codes from different samples are summed.

The distribution of information between cells of memory blocks 1-4 provides for any X and Y coordinates the ability to simultaneously write to four

Claims (1)

2x2 cells, with reference to the X, Y coordinates to the lower left cell of the square, as well as reading information with the maximum possible speed of following the samples at the input of the display 10, four times faster than a separate memory block 1-4. Invention Formula A device for displaying information containing the first, second. - Q 5 0 5 Oh, five 0 five 0 five the third and fourth RAM blocks, the luminance code sensor, the Y coordinate recording address generator, the X coordinate recording address generator, the TV scanning generator, the buffer memory block and the display unit, whose information input is connected to the output of the buffer memory block, whose clock input and the clock inputs of the display unit and the television scanner are the clock input of the device, the frame synchronization input of which is the frame synchronization inputs of the display unit and the The television scanner input, whose horizontal sync inputs are the horizontal sync input of the device, the first information input of which is the first information inputs of the X and Y coordinate recording address generators, the first output of the X coordinate recording address generator, is connected to the first address paths of the second and fourth operational blocks the memory, the second address inputs of which and the first address inputs of the first and third blocks of RAM are connected to the first output of the TV shaper a second sweep, the second output of which is connected to the second address input of the first and third address input of the second RAM, the control inputs of the first, second, third and fourth RAM, and the control input of the buffer memory are connected to the third output of the TV shaper sweep, the third address input of the first memory block is connected to the second address input of the third memory block, the third address input of which is connected to the third address input of the fourth b operating memory, the first output of the luminance code sensor is connected to the control inputs of the address formers of the X and Y coordinate records, characterized in that, in order to improve the accuracy of the device, it additionally contains the first, second, third and fourth multipliers, the control inputs of which connected to the second output of the brightness code sensor, the first pulse distributor, the outputs of which are connected to the first information inputs of the first, second, third and fourth multipliers, the outputs of which are connected respectively to the information inputs of the first, second, third and fourth blocks of RAM, the second pulse distributor, the first; the output of which is connected to the second i information inputs of the First, and the third multipliers, the second information the inputs of the second and fourth multipliers are connected to the second output of the second pulse distributor, the element NOT, the adder and the first and second switches, the information inputs of the first switch are connected respectively to the outputs the first, second, third and fourth blocks of on-memory memory, the outputs of the first switch are connected to the information inputs of the buffer memory block, the control input of the first switch and the input of the element are NOT connected to the second output of the television scanner, the output of the element is NOT connected to the third address inputs of the third and fourth memory blocks, the third address input of the first and second address inputs of the third memory blocks are connected to the output of the adder, the first information input of which connected to the first output of the write address coordinates X, whose second output is connected to the second information Jl Step 0 five 5 o 0 the adder input, the first information input of the second switch, the control input of the second pulse distributor, and the first information input of the first pulse distributor, the second information input of which is connected to the first output of the address generator of the recording coordinate Y, the second information input of which is the second information input of the device the third information input of which is the second infrmation input of the X coordinate recording address generator, the third output of which is connected to the second information input formation input of the second switch, the first control input of the first pulse distributor, the second control input of which and the first control input of the second switch are connected to the second output of the t coordinate recording address generator, the third output of which is connected to the third information input of the second switch, the first, second, the third and fourth outputs of which are connected respectively to the fourth address inputs of the first, second, third and fourth blocks of RAM, the information input of the second a pulse distributor coupled to the fourth output of the address' forms coordinates X. one Jl BUT one D. BUT T T FIG A