SU1432458A1 - Self-adjusting regulator - Google Patents

Abstract

The invention is intended for use in a heating control system and can be applied in metallurgy, chemistry, aviation. The purpose of the invention is to improve the accuracy of control. The parameters of the regulator are determined during the control of the gradient b method with a variable step multiplier of the control object lag taking into account the inertia of the control object. The delay of the control object is found by determining the instant of response of the control object to a rectangular impulse generated by the Generator and the Impulse Heater. 1 il.

Description

4ii

GS IvD

The invention is intended for use in a heating control system and can be applied in metallurgy, chemistry, aviation.

The purpose of the invention is to improve the accuracy of control.

The drawing shows a block diagram of a self-adjusting controller.

The self-adjusting controller contains a temperature sensor I, a temperature reference 2, an element. 3 comparisons, the first integrator 4, the first differentiator 5, the first 6, the second 7 and the third 8. multiplication blocks, the first summing amplifier 9, the third amplifier 10, the actuator 11, the second differentiator 12, the comparator 13, the first 14 and the second 15 pulse delay units, first element OR 16, first element AND 17, pulse generator 18, trigger 19, pulse shaper 20, second element 21, second element OR 22, counter 23, third element OR 24, third element And 25, digital-to-analog converter (DAC) 26, the second block 27 of the time delay, the third su the muting amplifier 28, the second integrator 29, the seventh multiplication unit 30, the first time delay unit 31, the second summing amplifier 32, the first dividing unit 33, the third differentiator 34, the fourth multiplication unit 35, the second quad 36, the sixth 37, the fifth 38 and the eighth 39 multiplication blocks, third 40, first 41 and fourth 42 quadrants, fourth summing amplifier 43, fourth differentiator 44, nine 45, tenth 46, eleventh 47, fourteenth 48, sixteenth 49 and fifteenth 50 multiplication blocks, third 51, fourth 52 and fifth 53 integrators, summing up five The second amplifier 54, a twelve multiplication unit 55, a sixth summing amplifier 56, a thirteenth multiplication unit 57, a seventh summing amplifier 58, and a second dividing unit 59,.

The self adjusting controller works as follows.

Signals arrive at the input of the reference element: the first from the temperature setpoint, the second from the temperature sensor. The difference of these signals (t) is fed to the first input of the third multiplication unit, the input of the first differentiator, the input of the first integrator

The second input of the third multiplication unit receives the signal K. (t + 2) from the output of the third integrator. At the output of the third multiplication unit, a signal is generated that is proportional to

K, e (t).

from the output of the first differentiator, the signal (t) is fed to the first input of the second multiplication unit, the second input of which receives the signal K (t + C) from the output of the fourth integrator, and a signal proportional to K (t +) (t) is formed at the input of the block

From the output of the first integrator, the signal (t) dt goes to the first input

about

the first multiplication unit, the second input of which receives the signal K j (t + Z) from the output of the fifth integrator, and the output of block 6 produces a signal proportional to t

Kj (t + 1) 5 E (t) dt,

From the outputs of the first, second, and third blocks of multiplication, signals are fed to the inputs of the first summing amplifier, from the output of which the signal proportional to

U (t) K, (t -t- t) (t) +

+ K (t + t) (t) + Kj (t + t;) JE (t) dt,

about

arrives at the input of the amplifier 10, and from its output - to the executive element 11,

The generator 18 generates continuous direct pulses, which from its output arrive at the first input of the element 17. If there is an enable signal at the second input of the element 17, which comes from the output of the element 16, the pulses appear at the output of the element 17. The first pulse from the output of the element 17 translates the trigger 19 into a single state. Trigger 19 triggers the pulse generator 20 to start and pulses through element 21 to the counter 23. The pulse from the pulse generator 20 is fed to the input of the first summing amplifier 9, which is summed with the main control signal of the controller.

The moment of response of the control object to a square pulse determines

c with the HELP of the second differentiator 12, the input of which is connected to the output of the temperature sensor 1, and the comparator 13, the input of which is connected to the output of the differentiator 12. To eliminate the appearance of a false signal at the output of the comparator 13, a signal equal to (T.jg ) ya on the control panel. The impulse from the output of the comparator 13 comes into the second input of the trigger I9 and transfers it to the zero state. At the same time, the pulse from the output of the comparator 13 goes through element I6 to the second input of element 17. As a result, the pulse from the generator 18 to the trigger 19 and the element 21 is prohibited. The pulse from the output of the comparator 13 after passing through the first block 14 of the pulse delay goes through element 24 the second input of the element 25. The code from counter 23 is copied to the register of the digital-analog converter 26, the latter converts the code to a voltage proportional to time 1, determined by the inertia of the control object. A pulse from the output of the first pulse delay unit 14 is fed to the input of the second pulse delay block 15, the output pulse of which converts the triggers of the counter 23 to the zero state. After resetting the counter 25, the determination process can be repeated.

The duration of the delay pulses is selected when setting up the circuit. Before starting the operation of the regulator, the inputs of the elements 22 and 24 are pulsed to zero the counter 23 and the digital-to-analog converter 26. To start the circuit in a definite time. Not ll, determined by the inertia of the control object, is fed to the input of the element 17 by a trigger signal in the form of a constant single signal. Z determination schemes using pulses Reset the counter and Write to the DAC register is reset to its original state before starting work.

five

Q o

From the output of summing amplifier 9, the signal U (t) is fed to the input of time delay unit 31 and the first input of summing amplifier 32, the output of which produces a signal proportional to the difference U (t) - U (t - f,).

The inputs of the first dividing unit 33 receive signals from the outputs of amplifiers 28 and 32. At the output of the first dividing unit 33, a signal is produced that is proportional to

IllKi t} (t) ()

JU

u (t) - u (t

- P.

)

from the output of the comparison element 3, the signal (t) is fed to the input of the quadrant 36, from the output of which the signal E (t) is fed to the first input of the multiplication unit 37, to the second input of which, the signal

II (Kjlt)

ei

proportional to the output of the first block 33 division. At the input of block 37, a signal is generated,

5.t (kji.t)

 aici

the stroke of the comparison element 3, the signal 5 (t) is fed to the input of the third differentiator 34 and the second input of the multiplication unit 35. From the output of the third differentiator 34, the signal (t) is fed to the first input of the multiplication unit 35, at the output of which a signal (t) is formed. f (t). The inputs of the multiplication unit 38 receive signals from the outputs of the units 33 and 35.

At the output of multiplication unit 38, a signal is generated proportional to

--- Tf-- ((- fe d to yi

From the output of the comparison element 3, the signal (t) is fed to the input of the second integrator 29 and the second input of the multiplication unit 30, the first input of which receives the signal J (t) dt from the output of the second integrator 29. The output of the multiplication unit 30 produces a signal

(t) S (t) dt.

From the output of the sensor 1 temperature signal proportional to Tg (t), is fed to the input of block 27 time. delays and the first input from the micro amplifier 28, the output of which produces a signal proportional to the difference Tg (t) - Tg (t - -2).

five

The inputs of the multiplication unit 39 receive signals from the outputs of the units 30 and 33. At the output of the unit 39, a signal is generated that is proportional to

 ) R., h iTilKjitb,

iv, j

-EK

3

ai

“(T) dt.

From the output of block 37, the signals are fed to the input of the quadrant AO, the output of which

1Ж:

From the output of block 38

mind / -5 si

signal ()

the sheath enters the entrance

quad 41, at the output of which 2 the signal (; -) is broken. From the exit

c kj

the eighth multiplier 39, the signal is fed to the input of the quadrant 42, the output of which produces a signal

The signals from the outputs of blocks AGf ---) 2 5K /

42 are fed to the inputs of summing amplifier 43, the output of which produces a signal proportional to 3

U ()

,

five

proportional

(fl) dK /

From the output of block 43, the signal arrives at the first input of block 55, multiplying the second input of which receives a signal from the output of a digital-to-analog converter, proportional to 2. At the output of block 55, a signal is generated,

3

I

from the output of block 37, the signal is fed to the first input of block 48, multiplying the second input of which receives a signal proportional to-K). At the output of block 48, a signal is generated

ZF.

 T - K, C block 38 output signal OK 1

steps to the first input of multiplication unit 49, the second input of which receives a signal proportional to K. At the output of unit 49, a signal is generated (9F).

 the output of block 39, the signal is fed to the first input of block 50, multiplying the second input of which receives a signal proportional to kj. At the output of block 50, a signal is generated

- - ЗК / 3

From the outputs of blocks 48-50, signals are fed to the inputs of summing amplifier 54, at the output of which image 3f.

signal - Z, --- K.,

iil dK; one

from the output of the quadrant 36, the signal is fed to the input of the differentiator 44, the output of which forms the signal f, to the inputs of the summing amplifiers from the outputs

56 is formed

tel 56 come in blocks 44 and 54,

Output amplifier

 $ F, 4 t signal - - Z --K.,

The signals from the outputs of blocks 26 and 56 are fed to the inputs of block 57 multiplying, the output of which is formed

F

-G signal - 1-, to the inputs of summing with t

amplifier 58 receives signals from the outputs of blocks 36 and 57. At the output of amplifier 58, a signal is formed that is proportional to 94.

national

FoC + - a t

which pos0

five

0

five

0

five

0

five

stupid on the first input of the second block 59 division, on the second input of which

  ZF .2 signal t, 2- (---) from the output

 .one

block 55, the output of block 59 produces a signal proportional to

) (t.o (f |; / 4/4

which is fed to the second inputs of multiplication blocks 45-47.

At the first input of block 45 multiply F

NIN signal - --- from the output

5K,

block 27 multiply. The output of block 45 is a signal), which is fed to the input of the integrator 51, the output of which produces a signal + S), which is then fed to the second input of block 8 multiplication.

At the first input of block 46 multiply

signal arrives - --- from the output of the block

ka 38 multiply. The output of the block .46 produces a signal K (t + C), which is fed to the input of the integrator 52, the output of which forms the signal K / j (t + C), which is then fed to the second input of the multiplication unit 7, To the first input of the block 47 multiply

af

signal arrives - --- from the output of forks}

ka 39 multiply. The output of block 47 produces a signal K, (t), which is fed to the input of the integrator 53, the output of which produces the signal K. (t + 2), which is then fed to the second input of block 6 multiplication. Determination of the parameters of the controller

K, (t + C),

Kjct

i)

Kj (t

) at

the control process, taking into account the inertia of the object, the gradient method with a variable step factor allows to increase the control accuracy,

Claims (1)

Claims of the invention A self-regulating controller containing a temperature sensor and a setpoint. Q is the twelfth multiplication unit, the temperature follower, the serially connected reference element, the first differentiator; the second block, multiply HIL, the first summing device, the amplifier, 5 tel connected by the output to the input of the divisible second division block, and the fourth differentiator, the fourteenth the multiplication unit, the fifteenth multiplication unit, the sixteenth unit with a multi-executive element, connected in series first. the integrator and the first multiplication unit, the temperature setter is connected to the non-one the reference input of the reference element, the output of the temperature sensor is connected to the inverting inputs of the comparison element, the output of which is connected to the input of the first integrator, the first input of the third multiplication unit, and the outputs of the first, second, third multiplication blocks are connected to the corresponding inputs of the first summing amplifier. and, in order to improve the control accuracy, it includes the first and second division blocks, the second differentiator connected in series, the comparator, and the first pulsed delay block. ki, second pulse delay block, serially connected first OR element, first AND element, sequentially connected trigger and pulse shaper, serially connected second AND element, counter, third AND element and digital-analog converter, and serially connected first time delay block and the second summing amplifier, the successively connected second time delay block, the third summing amplifier connected by the output to the input of the divisible first dividing unit, will follow flax connected third differentiator, the fourth multiplier, n tsh multiplier, a first squarer, serially connected second squaring, multiplying the sixth block, the third squarer, n- nye serially connected second integrator, multiplier seventh, eighth multiplier, the fourth squarer, posledovatel20 neither the second and third elements OR, thirty 35 the generator, the outputs of the third and seventh summing amplifiers are connected to the inputs of the dividend, respectively: the first and second division blocks, the output of the temperature sensors is connected to the input of the second differentiator, the output of the comparator is connected to the first input of the first OR element and the second trigger input, the output of which is connected to the first input of the second element And, the second input of which is connected to the output of the first element And, the output of the first pulse delay block is connected to the third input of the first element 1ShI, the input of the third element IL And, the output of which is connected to the second input of the third element And, the output of the second pulse delay unit is connected to the input of the second element OR, the output of which is connected to the second input, the score is -1ik, and the generator output is connected to the second input of the first element And, the output of the pulse generator 1 is connected to the input of the first is summed; its amplifier; the output of the digital-to-analog converter is connected to the second input of the twelfth multiplication unit and the second input of the thirteenth multiplication unit; the input of the second time delay unit is connected to the output The sensors and temperature pervp- input of the third summing amplifier, the output of the first summing amplifier is connected to the input of the first time delay unit and per- input of the second summing amplifier, whose output is connected to the input of the first divider dividing unit, whose output is connected to vtory40 45 50 65 but connected ninth multiplication unit, third integrator, successively. the tenth t-puzheny block and a quarter integrator, the eleventh multiplication block and the fifth integrator, the fourth back-up amplifier and successively connected fifth summing amplifier, sixth summing amplifier, thirteenth multiplication unit, seventh summing power20 neither the second and third elements OR, 0 five the generator, the outputs of the third and seventh summing amplifiers are connected to the inputs of the dividend, respectively: the first and second division blocks, the output of the temperature sensors is connected to the input of the second differentiator, the comparator output is connected to the first input of the first OR element and the second trigger input, the output of which is connected to the first input of the second element And, the second input of which is connected to the output of the first element And, the output of the first pulse delay block is connected to the third input of the first element 1ShI, the input of the third element IL the output of which is connected to the second input of the third element And, the output of the second pulse delay unit is connected to the input of the second element OR, the output of which is connected to the second input, the score is -1ik, and the generator output is connected to the second input of the first element And, the output of the pulse generator 1 is connected to the input the first is summed; its amplifier; the output of the digital-to-analog converter is connected to the second input of the twelfth multiplication unit and the second input of the thirteenth multiplication unit; the input of the second time delay unit is connected to the output d the temperature of the first and the first input of the third summing amplifier, the output of the first summing amplifier is connected to the input of the first time delay block and the first input of the second summing amplifier, the output of which is connected to the input of the divider of the first dividing unit, the output of which is connected to the second five 0 five The inputs of the sixth, fifth and eighth multiplication blocks, the output of the comparison element are connected to the input of the second integrator, the second input of the seventh multiplication unit, the input of the third differentiator, the second input of the fourth multiplication unit, the input of the second quadrant, the output of which is connected to the input of the fourth differentiator and the second input the seventh summing amplifier; the output of the fourth differentiator is connected to the second input of the sixth summing amplifier; the output of the sixth multiplication unit is co-15 multiplication unit, the output of which is En with the first inputs of the ninth and fourteenth multiplication units, the second input of the ninth multiplication unit is connected to the output of the second dividing unit, the output of the ninth multiplication unit is connected to the second input of the fourteenth multiplication unit, the output of which is connected to the second input of the fifth summing amplifier, the output of the fifth multiplication unit is connected to the first inputs of the tenth and sixteen the second multiplication unit, the second input of the tenth multiplication unit is connected to the outputs of the second division block, the output of the tenth multiplication unit is connected to the second input of the sixteenth multiplication unit, the output of the eighth multiplication unit is connected to the first inputs of the eleventh and fifteenth multiplication units, the second input of the eleventh multiplication unit connected to the output of the second division unit, the output of the eleventh multiplication unit is connected to the second input of the fifteenth dinene with the third input of the fifth summing amplifier, the outputs of the first, third, fourth quadrants are connected to the inputs of the fourth summing amplifier, the output of the twelfth multiplication unit is connected to the input of the second divider of the dividing unit, the outputs of the third, fourth, fifth integrators are connected to the second inputs of the third, the second and first multiplicators.