SU1429283A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to radio engineering and communications and can be used in measurement technology for synthesizing a reference signal. The purpose of the invention is to reduce the time setting frequency of the output signal. The frequency multiplier contains subtractor 1, accumulating adders (not) 2, 3, DAC 4, low pass filter 5, control oscillator 6, decoder 7, keys 8, 9. Number codes N ,, N are respectively sent to HC 2, 3. These codes determine the coefficient. multiplying the multiplier by tL (). Input pulses coming through key 8 in NS 2 accumulate in increments N ,. In HC 3, the output signal pulses, received through the key 9, accumulate with a step of N. In the subtractor I, the accumulated sums are subtracted. Difference Code (CR) d. the input signal pulse is increased by the value of N ,, and the output signal pulse is reduced by the value of N2. The frequency of the controlled oscillator 6 is tuned to the RC. The tuning occurs until the accumulation rate in the HC 2, 3 is equal. The RC can vary within О d, M, where n is the number of bits at the output and read 1. The decoder 7 closes the key 8 and opens the key 9 at .M, closes the key 9 and opens the key 9 when О d; NI and opens the keys 8, 9 at. N d.M-K ,. Such a formation of the CD eliminates the breakdown of synchronism at the boundaries of the range of jump-wise decrease. Sheni KR. 1 il. (L 0 from to 00 with

Description

The invention relates to radio engineering and communications and can be used in measurement technology for the synthesis of a reference signal in synchronous cystems for monitoring the status of rotary machines.

The aim of the invention is to reduce the time setting frequency of the output signal.

The drawing shows a structural; | electrical multiplier circuit often 1 | N

The frequency multiplier contains the subtractor 1, the first and second accumulating nfie adders 2 and 3, the digital-to-analog converter 4, the filter 5 of the lower clock, the control generator 6, the decoder 7, the first key 8, and the second key 9.

: The frequency multiplier works as follows |

I The information inputs of the first Q of the second accumulating adders 2J and 3 are given codes of numbers, respectively, N and N, which determine the multiplication factor of the frequency multiplier.

K-

For each pulse of the input signal, entered through the first key 8 to the control input of the first accumulating adder 2, the last c) summarizes the previously accumulated number with the number K, i.e. accumulation with step N. For each pulse of the output signal, received by 1Sh, through the second key 9 to the control input of the second accumulating adder 3, it is accumulated in steps of N. Subtractor 1 subtracts the second from the first accumulated sum, then the pulse of the input signal increases the current value of the difference code d- at the output of the reader 1 by the value of N, and each pulse of the output signal decreases it by the value of 1. The difference code after conversion by the analog-to-digital converter 4 to analog voltage through a filter 5 enters the control input of the controlled oscillator 6 and adjusts its frequency until the accumulation rates in the first and second accumulating adders 2 and 3, i.e.

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or

f f to f

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Difference code d. at the output, subtractors 1 can vary within

O d; M,

50

five

0

five

, „.

0

five

where, n is the number of bits at the output of the subtractor 1. The decoder 7 controls the first and second keys 8 and 9 in such a way that with M-N: d-M the first key 8 is closed and the second key 9 is open, with O d; - N-z the second key 9 is closed, and the first key 8 is open, with N d; The M-Ns are open to the first and second keys 8 and 9. Thus, at the boundaries of the range of a jump-like change of the difference code leading to a breakdown, no reduction occurs, which contributes to a reduction in the frequency of the output signal when the frequency of the signal at the frequency multiplier input changes.

Claims (1)

Invention Formula A frequency multiplier comprising a serially connected first accumulating adder, a subtractor and an analog to analog converter, a serially connected low pass filter and a controlled oscillator, and a second accumulating adder whose output is connected to the second subtractor input, characterized in that, in order to reduce the establishment time frequencies of the output signal, a delimiter was entered, as well as the first and second keys, while the outputs of the first and second keys are connected to the control inputs, respectively, ne first and second keys are connected to the first and second outputs of the decoder, the input of which is connected to the output of the subtractor, the output of the digital-to-analog converter is connected to the input of the low-pass filter, the information input of the second key is connected to the output of the controlled generator, and the information input of the first key is the input of the frequency multiplier.