SU1425678A1 - Device for approximate computation of inverse value of normalized binary fraction - Google Patents

Abstract

The invention relates to arithmetic devices with the control of digital computers, allows the calculation, control, and correction of approximate values of the reciprocal of a normalized binary fraction. The purpose of the invention is to increase reliability. The goal is achieved by the fact that the device containing the register of 1 argument, register 2 of the control code, subtractors 5 and 7, the group of elements EXCLUSIVE OR 6, the element AND-PE 8, the element OR-NO 9, the node convolution 11 modulo three and 13 comparison, contains an element NOT 3, an element EXCLUSIVE OR 4, a group of elements PERFORMING OR 10, and a trigger 12 with corresponding links. 1 il. f

Description

The invention relates to computing and can be used with. creating computer arithmetic devices.

The purpose of the invention is to increase the reliability of the device.

The drawing shows a diagram of the device for approximate calculation of the inverse of the normalized drodel fraction. The device contains a register of 1 argument, register 2 of the control code, the item is NOT 3, the item is EXCLUSIVE SHSh 4, the first subtractor 5, the first group of items EXCLUSIVE SHSh 6, the second subtractor 7, the item AND-NO 8, the item SH-NOT 9, the second group elements EXCLUSIVE OR 10, modulo three convolution node 11, trigger 12, comparison circuit 13, device argument code 14, device sync input 15, device control code input 16, device 17 information output, and device control output 18,

Recalculation of the reciprocal of the normalized binary fraction is performed in the device on the values of signals inverse to those on which the device malfunction was detected. This ensures that the re-computation is insensitive to a device failure and leads to the correction of an incorrect result.

The device works as follows.

At the beginning of the cycle, the forward code of the normalized binary fraction (starting with the second most significant bit) and its control code, respectively, are entered into register 1 argument and register 2 of the control code, respectively, and the forward code value is written into the even bits of the register 1 argument, and odd bits - inverse, code value. In the first and second bits of register 1, the argument is entered, respectively, the values of logical O and 1, which determines the inverse and direct values of the high bit of the code of the normalized fraction. The control code of the argument is defined as the result of convolution by a numeric modulus of three binary fraction codes, if the number of its digits n is odd. For an even code, the check code is defined as the result of the convolution modulo three

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(n-1) -h low bits of the binary fraction code. Writing to registers 1 and 2 is triggered by clock signals clocking the operation of the device. The clock signals are fed to the synchronous inputs of registers 1 and 2, as well as to the synchronous input of the trigger 12 through the synchronous input 15 of the device.

From the output of the second bit of register 1 argument, a single value is removed, which is fed to the first, second and seventh bits of the input of the decremented and second bits of the input of the first subtractor 5 to be subtracted 5. In addition, this single value is fed to the inputs of the first 5 and second 7 loans subtractors and the input element is NOT 3, from the output of which the zero value goes to bits from the third to the sixth and from the eighth to (n + + 2) -th input of the decremented and to the first discharge of the subtracted first subtractor 5, and also to the bit dy from first to fourth stroke subtrahend second subtracter 7. Thus on minuend input of the first subtractor 5 is formed constants code 3 + 2.

From the outputs of the even bits of register 1 of the argument, the direct binary fraction code shifted by one bit towards the higher bits goes to the first subtracter 5, where it is subtracted from the constant value 3 + 2. The third to nth argument code bits come from the register 1 argument outputs also to the first inputs of the first group of elements EXCLUSIVE 1 SKH 6-1, 6-2, ..., 6- (p-2). The second inputs of these elements through element 4 are supplied with the second digit of the argument code y, having weight 2, With a zero value of the bit, the code from the first inputs of elements 6-1, 6-2, ..., 6- (p-2) is transmitted their outputs are unchanged, and with a single value, the code is inverted. The resulting code From the outputs of the first group of elements EXCLUSIVE OR 6-1, 6-2, ..., 6- (p-2) is fed to the input of the deductible subtractor 7, to the input of which is reduced, the difference code from the output of the first subtractor 5 is received. Thus , at the output of the reader 7, an approximate value of the reciprocal of the normalized binary fraction is formed, which is determined by the formula

Y, (3 + 2 - 2X) - S interval 0.5 X. one,

X - 2, if 0.5: 6 X "0.75, where 5, 1 - (X + 2), if 0.75" X 1 1.

From the output of the second subtractor 7, the code of the reciprocal of the value of the normalized binary fraction enters without change through the elements EXCLUSIVE OR 10-1, 10-2, ..., 10- (n + 2) of the second group on the output 17 of the device.

Nodes 2, 8, 9, 11, and 13 control the calculation of the reciprocal of the normalized fraction. The control is based on the ratios that take place in the approximate formula between the values calculated from it and their divisibility by three. Residues from division into three 1 and 2 are encoded respectively 01 and 10, the remainder of O has two representations 00 and 11.

(one)

On the interval 0.5 mules (1) has the form

 X - i 0.75 odds-5

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Y 3-3X- -2 +2

Taking into account, then for odd | 1x values of K 3 2, 3 -1,

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Ymod.

On the interval 0.75 X 1, formula (1) has the form

Y 2 - X -I- 2 + 2. For odd n Ymod 3 -Xtnod 3..

For even n, taking into account that for even values,

Ymod 3 - (X - 2) mod 3.

The value (X-2) mod 3 can be defined as the result of a convolution modulo three (n-1) -bh low bits of the code X of a normalized binary fraction.

Thus, the control code is determined, which is written in register 2 of the control code for even n. If n is odd, then the result of the convolution modulo three of the whole X code is the control code.

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Weight functions of the first and second

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The bits of the control code are respectively 2 mod 3 1 and 2 mod 3 with 1, i.e. equal in magnitude and opposite in sign.

At zero value of the correction, the outputs of elements 8 and 9 take the values 1 and O, respectively, that

10 corresponds to the code Ymod 3 1 on

the range of 0.5 X - 0.75. With a single bit value, the elements 8 and 9 invert the values of the control code bits, i.e. The code Ymod 3 -Xmod 3 or Ymod 3 - (X-2) mod 3 is detected from their outputs, defined in the interval 0.75 X 1. From the outputs of elements 8 and 9, the code Ymod 3 is fed to the input of the first number 20 of the comparison circuit 13 . The input of the second number of the comparison circuit 13 is the result of the convolution of the approximate

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Y values generated by modulo three convolution node 11. Comparison of the specified codes leads to the determination at the output 10 of the device of the control signal that takes a zero value when the device is functioning properly. A single value indicates a device fault.

 Evils 10-1, 10-2, ..., 10- (n + 2) and 12, as well as the argument register 1, are used to correct the result at the output 17 of the device when it is established that it is incorrect: functioning. In this case, the output of the comparison circuit 13 takes a single value, which in addition to outputting to the control output 18 of the device also goes to the information input of the trigger 12, to the input of the register 1 mode of the argument and the lock input of the recording of the register 2 of the control code. In this case, in register 2 of the control code, the recording of a new control code is blocked, which is performed at the beginning of each clock cycle according to clock signals at a zero value at the input of the record lock. In register 1 of the argument, the write mode changes to the shift mode, and with the arrival of the clock pulse, information is shifted by one position, as a result of which the output of the even bits of the register 1 argument is the inverse code

55 arguments (previously written in odd bits of register 1). At the output of the trigger 12 with the arrival of the clock pulse, a single value is set.

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which arrives at the second inputs of the elements EXTENDING OR 10-1, 10-2 .. o, 10- (n + 2) groups, as well as element 4, ensuring that the signals at their first inputs are inverted at the outputs of these elements.

The occurrence of the inverse argument value at the outputs of the even bits of the register 1 leads to the establishment at all inputs and outputs of the first 5 and second 7 subtractors of the values of signals inverse to the values that should have received these signals at the previous clock cycle, marked by incorrect operation of the device . The output of the second bit of register 1 argument and the output of the NOT 3 element are set to zero and one values, respectively, which change to the inverse values of the signals at the inputs of the first 5 and second 7 subtractors at all input bits of the decremented and two high bits of the input of the deductible first subtractor 5, as well as on the four higher bits of the input of the subtracable subtractor 7. For the lower entry bits of the subtracable subtractor 5 and to the first inputs of the elements EXCLUSIVE OR 6-1, 6-2, ..., 6 ( -2) groups come directly pa h-: p is the dy of the inverse argument value. The output of the EXCLUSIVE OR 4 item does not: change the direct value of the bit ijr, because this bit is subjected to double inversion first: when shifting the register of argument 1, a, and then on the element 4. Under the action of the direct value of the bit, the inverse code ( The p-2) -h low bits of the argument are transmitted through the elements EXCLUSIVE OR 6 of the first group (without change or with inversion - in accordance with the code translation rule for the previous cycle) and arrive at the (p-2) -bh low entry bits deductible second subtractor 7.

When processing the direct value of the argument, a single value enters the inputs of the loan of the first 5 and second 7 subtractors, ensuring the execution of the subtraction operation in the additional code. When processing the inverse value of the argument on all the inputs of the first subtractor 5, the signals change their values to inverse, which leads to the generation at the outputs of the first subtractor 5 of the code, inverse

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in relation to the code that should have been received on the previous .tact. This code, in turn, will ensure the establishment of inverse values at the input bits of the decremented second subtractor 7 and, accordingly, at its output. Next, the code from the output of the second subtractor 7 is inverted on the elements EXCLUSIVE OR 10-1, 10-2, ..., 10- (n + 2) of the second group and the result obtained is the inverse of the normalized binary fraction at the output 17 of the device.

Nodes 2, 8, and 9 that perform the control under the action of an immutable direct bit value are computed at the inputs of the first number of the comparison circuit 13 the previous value of the Ymod code 3. The input of the second number of the comparison circuit 13 receives the result of convolution modulo three of the newly calculated inverse - the value of the normalized binary fraction. The comparison circuit 13 determines the new value of the control signal.

Claims (1)

Invention Formula Device for approximate calculation of the reciprocal of a normalized binary fraction containing the argument register, the first and second subtracters, the control code register, the first group of (n-2) elements EXCLUSIVE OR, a convolution node modulo three, the AND element, the element OR-NOT and the comparison circuit, with the input of the i-ro bit of the device argument connected to the information input of the 2 i-ro bit of the register of the argument (i 2n, n is the number of bits of the argument), the output of the 2 i-ro bit of the register of the argument connected to the input (i + 1) -ro bit of deductible first The reader, the output of the 2K-th bit of the register of the argument (K 3, .. n) is connected to the first input of the (K-2) -th element of the EXCLUSIVE OR of the first group, the output of which is connected to the input of the (K + 2) -th bit of the deductible the second subtractor, the second inputs of the EXCLUSIVE OR elements of the first group are combined with each other, the inputs of the first, second and seventh bits of the decremented and the input of the second discharge of the subtracted first subtractor are combined with each other, the inputs of the bits from the third. ) -2) -and decreasing the first time, the inputs of the pehovogo and (n + 2) th bits of the readable first subtractor, as well as the inputs of the four most significant bits of the readable second subtractor are interconnected, the output of the first subtractor is connected to the input of the decremented second subtractor, the information output of the device is connected to the input of the convolution node modulo three, the input of the control code of the device is connected to the information input of the register of the control course, the first input of the AND element is NOT connected to the inverse first input of the OR-NOT element and to the second inputs of the EXCLUSIVE OR elements of the first group, the output the first AND second bits, the control course register are connected respectively to the second inputs of the AND-NOT and OR-NOT elements, the outputs of which are connected to the input of the first number of the comparison circuit, the input of the second number of which is connected to the output of the convolution node modulo three, the output of the comparison circuit The control output of the device, the sync input of which is connected to the synchronization inputs of the argument register and the control code register, is characterized in that, in order to increase reliability, it contains the element NOT, the element EXCLUSIVE OR, trig the hero and the second group of (n + 2) elements are EXCLUSIVE OR, and the information input of the 2i-ro bit of the register of the argument is connected to the inverse five 0 five 0 five information input (2i-1) -ro bit register register arg. The information inputs of the first and second bits of which are connected respectively to the inputs of the logical zero and logical unit of the device, the output of the second bit of the register of the argument is connected to the inputs of the loan of the first and second subtractors, with the input of the first discharge of the decremented first subtractor and the input element is NOT, the output of which is connected to the input of the first bit of the readable first subtractor, the outputs of the comparison circuit are connected to the input of the lock of the record of the control code register, with the input of the setting of the mode of the argument register The input and with the information input of the trigger, the synchronization input of which is connected to the synchronous input of the device, the output of the fourth bit of the register of the argument is connected to the first input of the EXCLUSIVE element, or the output of which is connected to the second inputs of the EXCLUSIVE OR elements of the first group, the outputs of the second subtractor are connected to the first inputs of the corresponding elements of the MASTER OR OF the second group, the second inputs of which are combined and connected to the second input of the element of the MASTER CONCRETE OR or to the trigger output, the outputs of the elements SPARE AYUSCHEE second- OR groups are iyuformatsionnym output device.