SU1425676A1 - Device for checking parallel binary code by modulo k - Google Patents

Abstract

The invention relates to automation and computing and can be used to build various devices for processing discrete information. The purpose of the invention is to reduce the equipment of the device. The device contains a group of blocks 1 addition modulo K, an adder 2 L. J t ,, unitary CODES, a unit 3 convolutions modulo K, a group 4 informational INPUTS of the device, information OUTPUT 5 devices, a group of nodes 6 addition modulo K, a node 7 unitary codes, node 8 convolution modulo K, group of adders 9 modulo two, first group of multithreshold elements 10, group of elements 11, group of elements OR 12, second group of multithreshold elements 13. The result of adding the bits of the INPUT code modulo K as unitary code with output in blocks 1, the modulo K group enters the INPUTS of the adder 2 unitary codes. The result of the folding is folded by a convolution unit 3 modulo K, 9 Il. u ut

Description

The invention relates to automation and computing and can be used to build discrete information processing devices.

The aim of the invention is to reduce the hardware of the device.

Figure 1 shows the functional diagram of the device for monitoring a 24-rad code modulo K; FIGS. 2 and 3 are functional diagrams of embodiments of the addition unit modulo K; FIGS. 4 and 5 are the same; the block of addition modulo KJ in FIGS. 6-9 is the same of various multi-threshold logic elements.

A device for controlling parallel binary code modulo K; (Fig, 1) contains a group of blocks 1 of the modulo K unit, an adder 2. of unitary codes, a block 3 of convolution modulo K, a group of 4 information inputs of the device, an output 3 of the device i, a group of nodes 6 of addition - Gululu K, node 7 summation of unitary i codes, node 8 convolution modulo I K, group of adders 9 modulo: two, the first group of multithreshold I elements 10, the group of elements 11 and 11 the group of elements OR 12, the second; group of multithreshold elements 13. In FIGS. 2 and 3, the following notation is adopted: group of adders 14: modulo κ, first group 15 ele; cops And, the first group of elements: OR 6, two groups of multithresholds mx elements 17 and 18, the second group of elements And 19, the second group of elements OR 20, the group of adders 21 modulo two,.

Node 8 convolution modulo K (Fig, 4) contains a group of elements And 22 and a group of elements OR 23,

A device for controlling parallel binary code modulo K works as follows

When submitting to the information inputs of group 4 of the controlled code device, the unitary code of the number arriving at the inputs of the block is formed at the outputs of the addition blocks 1 modulo K of the group. In this case, it is carried out carrying each bit of the monitored code modulo K.

The signals from the outputs of the blocks of 1 modulo K group are fed to the inputs of the adder 2 unitary codes,

If in block 1. addition modulo K group (ZTco. X;) mods 1, it is j j

means that single signals are present on all outputs of the block with numbers. On the other outputs, there are zero signals (x. Is the value, j-ro of the controlled code connected to the input of block 1 of the modulo K group, with: - its weight modulo K),

The adder 2 unitary codes adds the input codes so that at its output a unitary code is formed, having units at the outputs with weights

five

0

0

so xOmodK)

1 v

R (AND (

/ ° where K is the number of blocks of 1 addition

modulo K in the group, Block 3 convolution modulo K converts the unitary code at the output of adder 2 into a unitary code, where the units

are in bits with weights

W. (21 to; x;) modK (n is the width

controlled code).

The node 6 addition modulo K (Fig, 2 and 3) is built on the same structure as the device as a whole and works in a similar way.

Claims (1)

Invention Formula A device for controlling parallel binary code modulo K, containing a group of addition blocks modulo K and a convolution block modulo K, the output of which is an information output of the device, characterized in that, in order to reduce the equipment of the device, it contains an adder of unitary codes, each of the addition blocks modulo K the group contains a convolution node modulo K, a summation unit of unitary codes and a group of addition nodes modulo K, and in the second addition block modulo K the group of information outputs of the nodes neither modulo K group is connected to the inputs of the corresponding addends of the summation node of unitary codes, the output of which is connected to the input of the convolution node modulo K, groups of information inputs of addition nodes modulo K group form a group of information inputs of the block, outputs of convolution nodes modulo K all blocks adding 31D256764 modulo K the group is connected to the input module K, the group of information dami terms of the adder unitary inputs of the addition blocks by modulus K codes, the output of which the group is the information connected to the input of the convolution unit of the device inputs. five Fa G. 2 FC9.3 Jjj   U p1 1 S "I: h F (/ 8 Fc 6 0-1 Fi 7