SU1425672A1 - Device for distributing tasks in multiprocessor computing system - Google Patents

Abstract

The invention relates to computing, in particular, to multiprocessor computing systems, and is intended to distribute the computational load among processors in such systems. The purpose of the invention is the expansion of the functional capabilities of the device due to the redistribution of tasks, taking into account their importance between efficient processors after the complete failure of one or several processors. The device contains a descrambler, a group of triggers, a memory block and a block for enumerating tasks. The enumeration block of tasks contains a group of registers, a group of triggers, five groups of elements AND, a generator of pulses, two elements OR, a group of elements OR, a delay element, a register and a ring shift register. The state of the processors is stored in the storage unit of the device. A processor failure message in the form of a failed processor code is input to the device. In this case, if the failed processor solved the main problem, device f transmits the code of this task to the healthy processor, which prior to fixing the failure was either in reserve or solved a minor problem. 1 il.

Description

The invention relates to computing, and specifically to multiprocessor computing systems; it is intended to distribute the computational load between

processors in such systems, i. The aim of the invention is to expand the functionality of the device due to the redistribution of I tasks, taking into account their importance among working processors after the complete failure of one or several I processors,

I The drawing is a block diagram of the device.

The device contains a group of code inputs of the device 1, a decoder 2, a bunch of flip-flops 3, a block 4 for sorting tasks, a group of outputs 5 of the device. The task enumeration unit 4 contains a generator of 6 pulses, a shift register I 7, a group of 8 elements AND, I element OR 9, a group of 10 registers, I group 11 elements AND, a group 12 I triggers, a group 13 elements AND, a block 14 elements OR, register 15, I group 16 elements AND, group 17 elements AND, element OR 18, element 19 I delays, All solvable computational systems i of the problem are divided into two groups: main and minor problems. In the event of a processor failure, the solution of the main task must be provided either by a backup processor (if one exists) or by transferring the main task to the processor, which is solved by a non-main task.

The device works as follows

The registers of the group 10 registers of the task enumeration unit 4 store the setup codes of the processors associated with these per-headers to solve certain tasks. At the initial moment of time (up to the first failure in the system), the setup code of the first processor is stored in the first register of the registers group 10 in the second register, the setup code of the second processor and t „d, in accordance with the initial distribution of tasks in the system. If the system has redundant processors; then in their respective registers of group 10, for example, a zero code is written,

Triggers 3 store information about the state of the system's processors,

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the initial moment of time when all the processors of the system are operational, the triggers of group 3 are signaled from the corresponding input of the initial installation of the device to one,

System processors periodically self-diagnose; when a failure is detected by any processors, the code of the failed processor is fed to the inputs of the device 1. At the corresponding output of the decoder 2, a logical unit appears, transferring the corresponding trigger 3 to the zero state.

The registers of group 10 correspond to the triggers of group 12. In the process of setting the initial conditions, the triggers of group 12, corresponding to the registers of group 10, in which the codes of the main tasks are entered, are transferred to one state; the rest of the triggers of group 12 are transferred to the zero state. In the future, the triggers of group 12 can only go from zero to one. This circumstance reflects the fact that only a redistribution of tasks is possible in the system, in which the transfer of the main task is possible only to the processor, the solving minor task, or to the processor that is in reserve.

At the output of the corresponding element AND of group 16, a logical 1 doctr. Is maintained for as long as the corresponding processor, which solves a nonbasic problem, or is in reserve, remains operable.

At the output of the AND element of group 17, logical 1 appears in the event that the failure of the corresponding processor that solves the OCHOBHJTO problem is detected.

When the initial conditions are specified, one of the bits of the ring shift register 7 is entered into logical 1, the remaining bits are reset to the zero state, I

Provided that the input of the resolution of the shift of the register 7 enters the logical O from the output of the element OR 9 with the arrival of the next pulse of the generator 6 to the synchronous input of the register 7 in the latter the logical 1 is shifted to the next bit. Thus, at each time logical 1 on

one of the outputs of the shift register 7, and the remaining outputs support logical O. From the output of register 7, logical 1 goes to the first input of the AND element of group 8. In the second input of this element I from the output of the AND group

16 Logic O arrives at the output of the AND element of group 8, logical O is maintained. At the outputs of all other elements of AND group 8, logical O is also supported, since logical inputs arrive at their first inputs.

About from the corresponding outputs of the register 7. Thus, at the output of the element OR 9 it is supported logically O and with the arrival of the next generator pulse 6, logical 1 from the register register 7 goes to the next bit of this register. The described process occurs until the output of one of the AND elements of group 8 generates a logical 1, which through the OR 9 element enters the resolution of the shift of the register 7 and thereby prohibits the further shift of the logical 1 in the bits of the register 7 .. At the same time, the output of the AND element of group 8 is also supported by logical 1. Such a situation is possible only if the output of the element of AND 16 of group 16 is supported by logical 1, which indicates that the corresponding processor remains operable and is either In a section, or solves a nonbasic task.

Suppose that in the system there is a failure of a processor that solves the main task. In this case, the corresponding trigger of group 3 is transferred to the zero state and at the output of the corresponding elements of the group

17 is a logical 1, which opens the corresponding AND element of group 13. As a result, the task code stored in the corresponding register of group 10, through block 14 of the elements OR, is fed to the information inputs of register 15. At the same time, logical 1 from the output element AND group 17 through the element OR 18 arrives at the delay element 19 and the input of the write enable register 15. In register 15, the main task code is fixed by the failed processor. After a time interval defined by delay element 19.

logical 1 from the output of the element OR 18 enters the second intervals of elements AND of group 11,

As noted above, in the group of 8 elements, AND logical 1 is supported only at the output of one AND element and arrives at the first input of the corresponding element AND of group 11. Therefore, with the arrival of logical 1 from the output of delay element 19, logical 1 appears at the output of AND element 11. The specified logical 1 resets the trigger of group 12 to the zero state and allows writing the output code of register 15 to the corresponding register of group 10. Thus, the main task code stored until the processor failed in the corresponding group register 10, is written to another register of the same group and goes to the outputs of group 5 of the device outputs. As a result, the code corresponding to the processor, which had been located before the failure of the other processor in the standby mode, or was solving a minor task, was transferred the code of the main problem, which was solved by the processor that had previously failed.

Resetting the trigger of group 12 to the zero state results in the appearance of a logical O at the output of the AND element of group 16, as a result of which, at the outputs of the AND element of group 8, as well as the element OR 9, logical O appear. With the arrival of the next generator pulse 6 into a single the state is set to the next bit of register 7, the logical 1 is fixed in this bit until the next failure of one of the processors, which solves the main problem, if the output of the corresponding -element AND group 16. logical 1 is maintained, which is the case if the corresponding processor is fixed and solves a non-core task or is in reserve. Otherwise, as described above, with the drive of each alternating pulse of the generator 6, logical 1 advances to the next bit of the shift register 7 until the logical 1 coincides at the inputs of one of the And elements of group 8.

Thus, in the device failures of processors are fixed and in case the failed processor solved the main task, the device transmits

The code for this task is a serviceable processor, which before fixing the failure in the system was either in reserve or solved a non-essential task.

Claims (1)

Invention Formula A device for distributing tasks in a multiprocessor computing system that contains a decoder, a group of triggers and a task enumeration unit, the group of code inputs of the device connected to a group of inputs of the decoder, each output of which is connected to the reset input of the same name trigger group, the task enumeration block contains a register , the group of registers whose outputs are groups of device outputs is about the fact that, in order to expand the functional capabilities of the device due to the redistribution of tasks with m of importance: between operable produ; essorami; after a complete failure of one or several processors, a group of triggers are entered into the block for enumeration of tasks, the first, second, third, fourth: groups of elements I, the generator of impulses: ow, group of blocks of elements AND, the first and second elements OR, block of elements OR, delay element and shift-: beef register, with the output of the generator; ra pulse connected to sync ; : SHIFT register whose outputs ; connected to the first inputs of the corresponding elements And the first group,; the outputs of which are connected to the first the inputs of the elements of the second group and The inputs of the first OR element, the output of the shift register connected to the shift input, the outputs of the elements of the second group are connected to the zero inputs of the triggers group of the task enumeration unit and the input inputs of the corresponding participants of the group of triggers, the unit inputs of the trigger group triggers tasks and informational inputs of the shift register are connected to a group of inputs. the initial installation of the device, the installation input in the first 1 bit of the shift register is connected to the output of its last bit, the zero outputs of the triggers group of the task search block are connected to the first inputs of the AND elements of the third group, the second inputs of which are connected to the outputs of the group triggers and inverse elements of the elements of the fourth group, the direct inputs of which are connected to the direct outputs of the triggers of the group of the task search block; the outputs of the elements of the fourth group are connected to the inputs of the second element OR whose output is connected en with the register entry resolution input and through the delay element - with the second inputs of the elements of the second group, the outputs of the elements of the third group are connected to the second inputs of the same elements of the first group, the group of outputs of each register of the group is connected to the group of information inputs of the same name block of elements AND of the group , the control input of each block of elements AND of the group is connected to the output of the element of the same name AND the fourth group, the outputs of the blocks of elements AND of the group are connected to the inputs of the block of elements OR, the group of outputs cerned is connected to a group of information inputs of the register, which output group connected to groups of the group of information inputs of registers. , L: fH.y.