SU1425609A1 - Multichannel control device for actuating mechanisms - Google Patents

Abstract

The invention relates to automation and can be used in various process control systems. It ensures the work of the possible Reliable increase from the highest levels, control unit 3, the unit with the mechs of the mechanics keeps me 8, the request for interrupting the operation of the actuators using arbitrary algorithms. The purpose of the invention is to increase the functionality and reliability of the device. The reliability of the proposed device is enhanced by eliminating interference from the high voltage circuits of the actuators 5 in the control device, as well as by assigning control codes permanently stored in memory 3 to the actuators 5. The device contains a decoder 1, driver 2, unit memory 3, pulse generator 4, amplifier with actuator 5, n control channels 6 actuators, each of which contains register 7, time generator 8, optoelectronic switches 9.4 Il. yo ya "(l with

Description

The invention relates to automation and can be used in various process control systems.

The purpose of the invention is to expand the functionality of the device and increase its reliability.

Fig. 1 shows a block diagram of a multichannel device controlling the actuators; in fig. 2 - block diagram of a shaper (programmable timer); FIG. 3 is a diagram of the imager pulses; FIG. 4 is a diagram of an optoelectric tpoHHoro key.

Multichannel actuator control device Consists of a decoder 1, generating 2 pulses, a memory unit 3 of the memory, a pulse generator 4, amplifiers with actuators 5 and actuator control channels 6, of which registers 7, the driver 8 time (programmable timer), optoelectronic keys 9, block 8 is built on the counter 10 pulses and register 11 modes.

The decoder 1 serves to select a time maker 8 or register 7 into which information from a memory device is to be recorded. The pulse former 2 is designed to pulse the recording of information into registers 7 and the driver 8 ,. .

The memory blocks are used to store the control codes of the actuators | anisms, which determine the sequence of operation of the amplifiers of each of the actuators, as well as the storage time codes in the register 7 of the control codes, the executive mechanisms,

A pulse generator 4 serves to generate a pulse of stable frequency.

Amplifiers of the actuators 5 serve to form currents in the windings of the actuators: the mechanisms of the signals arriving at their inputs from the outputs of the register 7,

Register 7 of the control channel

The integration mechanism serves to store the actuator control codes.

A time shaper 8 serves to form a storage time in

,

yu 15

20 25

30 h

40 5

0

five

Register 7 of executive control codes.

Optoelectronic switches 9 serve for galvanic isolation of signals from the outputs of registers 7 with the inputs of amplifiers of executive mechanisms 5,

In the example of a specific implementation, a stepping motor is selected as the actuator of the control channel in question.

In the initial state, the control channel register 7 is reset (the bus Reset of registers 7 is not shown), the stepper motor windings are de-energized, and the information of the actuator control channels is recorded in a memory device.

The device works as follows.

A code defining the operation mode of the control channel is written to the information controller 8 of the K-th control channel from a memory device (programmable driver 8 operates in such a mode that after loading it with some code, for each pulse received at its input from the generator of 4 pulses, the value of this code is reduced by one to zero, waiting for the new code value to load. This is implemented as follows.

The control unit inputs the address of the decoder 1 to the address of the corresponding driver 8 and the cell address of the memory block 3, in which the mode control code of the driver 8 is stored. The decoder 1 forms the resolving potential at the driver input from the output on the bus Sq (Fig. 1 and 2) 8. Simultaneously, at the address specified on the memory input, the read signal is read from the memory device via bus 13 and written to the register 11 of the modes of the programmable timer 8 with a pulse from the output of the driver 2 via the bus 12 code specifying p the counter 10 shaper 8,

Further, the control device according to the program outputs to the inputs of the decoder 1 and memory block 3, respectively, the register address 7 of the selected control channel of the stepping motor and the address of the cell in which the control code of the stepping motor is stored. The decoder 1 forms on the output bus ZK-2

SPHG.1) resolving potential

de register 7.

The read signal from the output of the memory device to the input of register 7 is transmitted via the bus 13 to the stepping motor control code.

Impulse from the shaper output

2 bus 12 reads data from the storage device and records are written to register 7.

From the output of the register 7, the code switches on the optoelectronic keys 9 and the amplifiers in the selected windings of the stepper motor.

The other control device outputs to the inputs of the decoder 1 and the block

Claims (1)

3, respectively, the address of the generator 8 of the selected control channel of the stepper motor and the cell address of the memory block 3 in which it stores When simultaneously receiving requests from several drivers 8, the control device serves the control channels of the actuators in accordance with their priority. Invention Formula Multichannel actuator controls, containing a pulse generator, a decoder and power amplifiers by the number of channels, as well as Address, Data, Read and Write input buses, characterized in that, in order to expand the functionality and increase the reliability of the device, a memory block, a pulse shaper, and control channel - time shaper name, register and optoelectronic key c code defining time selected state of the windings (time steps). Descrambler 1 forms bus ZK-1 (Fig. 1) the resolving potential for 25 bits of its register inlet shaper 8 time. channel output pulse generator chi, whose outputs are connected to the corresponding INPUTS of the power amplifiers, and the inputs to the corresponding The code from the output of the memory block 3 is impulse from the output of the driver 2 is written to the counter 10, which operates in the subtraction mode. When pulses are received from generator 4 via bus 14 to counter 10 in an amount equal to the code written into it (step time), it is set to the zero state. In this case, a register request signal is generated from the register output of the 11 programmable timer modes. By this signal, in the described manner, the control device writes new values of the code for turning on the windings of the stepping motor in register 7 and the code for the time of switching on the selected state into driver B from memory block 3. Thus, the process is repeated for each request. The other control channels of the actuators work in the same way. thirty connected to the first input of the form of time bodies of each channel, the second inputs of which are connected to the first input of the register in the control channel and to the output of the memory unit; the third inputs of the time drivers are connected to the second input of the register in the channel and to the output of the pulse former 35 owls, whose input is connected to the input bus Read and to the first input of the memory unit, the second input of which is connected to the input of the decoder and to W is not Address, bus Data and Record 40 are connected respectively to the third and fourth inputs of the memory unit, the outputs of the time drivers are connected to the bus interception request, and the fourth inputs to the corresponding first decoder outputs, the second outputs of which are connected to the third inputs of the register of the corresponding channel. the bit outputs of the register chi, the outputs of which are connected to the corresponding INPUTS of the power amplifiers, and the inputs to the corresponding connected to the first input of the time generator of each channel, the second inputs of which are connected to the first input of the register in the control channel and to the output of the memory unit; the third inputs of the time drivers are connected to the second input of the register in the channel and to the output of the pulse former, the input of which is connected to the input bus Reading with the first input of the memory block, the second input of which is connected to the input of the decoder and to the bus Address, bus Data and Record connected to the third and fourth inputs of the memory, respectively; the outputs of the time drivers are connected to the bus Interception request, and the fourth inputs to the corresponding first outputs of the decoder, the second outputs of which are connected to the third inputs of the corresponding channel register. fz 7 From SAOKU 7 FIG. 2 fig.Z On ffAOKS Fia