SU1425588A1 - Device for reading microfishes with automatic frame setting - Google Patents

Abstract

The invention relates to a photographic technique and can be used in reading or copy-reading oval apparatus. The purpose of the invention is to improve the quality of searching for the required microfiche frames. The device contains a reading head 1 for reading from the microfiche information about the content of its frames and their X, Y coordinates, electronic memory 2 read-write for storing the read information, an alphanumeric keyboard 3, an encoder 4 and a comparator 5, with the help of which input and coding the search prescription, as well as comparing it with the frame search images, two channels for controlling the position of the microfiche, each of which includes a group of elements AND 12 and 13, a device for storing the coordinates of frame 14, 15, digital analog A new converter 16, 17 and the following circuit 18, 19. Improving the quality of searching for desired microfiche frames is achieved by using a transform unit of 7 search instructions and by the search patterns commuting this block of multiplexer 6 and demultiplexer 8 with their RS trigger 11, which controls them, as well as two accumulating registers 9, 10 for storing the search image and search prescriptions that have been converted to a single form. 3 il. S (l

Description

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The invention relates to optical instrument making and can be used in projection devices of reading or reading and copying-ball type with change of pictures, which are located on a segment of film equipped with optically coded marks.

The purpose of the invention is to increase the quality of search for the necessary frames. I FIG. Figure 1 shows the structure of a device for reading microfiches with automatic frame setting; FIG. 2 is a diagram of a conversion unit; FIG. FIG. 3 shows the construction of an electronic read-write memory.

A device for reading microfiches with automatic frame setting (Fig. 1) contains a read head 1, an electronic memory 2 read-write, an alphanumeric keyboard 3, an encoder 4, a comparator 5, a multiplexer 6, a conversion unit 7, a de-multiplexer 8, accumulating registers 9 and 10 are RS-flip-flop 11, groups of N elements And 12 and 13, devices 14 and 15 of coordinate storage, digital-headed converters 16 and 17, and the following circuits 18 and 19.

Conversion unit 7 (Fig. 2) contains comparison circuits 20 and 21, groups of K and R circuits 22.1-22.K and 23.1-23.R comparisons, static registers 24 and 25, groups of K and R static registers 26.1-26 .K and 27.1- 27.R, group 28 of N elements AND, buffer register 29, counter 30 with decoder, RS-triggers 31 and 32, elements AND 33 and 34, AND-HE elements 35 and 36, elements OR 37- 42, delay elements 43-47 ,. groups 48 and 49 of N delay elements, block input 50, block outputs 51-53.

The elements of the microfiche reader with automatic frame setting are connected in the following way. The first and second outputs of the reading head 1 are connected respectively to the first and second inputs of the electronic memory 2 of the read-write, the input of the encoder 4 is connected to the first output of the alphanumeric keyboard 3, a group of N elements I 12, a coordinate memory device 14, digital-analog the converter 16, the following circuit 18 are connected in series, a group of N elements AND 13 a device 15 of storing the coordinates of a digital-to-analog converter 17 and

0 5 0

5 0 5

0

The following circuit 19 is also connected in series, the first inputs of groups of N elements 12 and 13 are connected to the output of comparator 5 and the fourth output of read-write electronic memory 2, and the second inputs are connected to the first and second outputs of electronic memory 2, respectively. read-write, the first input of the multiplexer 6 is connected to the output of the encoder 4, and the second to the third output of the electronic read-write memory 2, the output of the multiplexer 6 is connected to the input of the element 46 of the conversion unit 7, the outputs of the elements 47-49 are connected but with the first, second and third inputs of demultiplexer B, the fourth and fifth inputs of which are connected respectively to the third and fourth inputs of multiplexer 6, the first and second outputs of the RS flip-flop 11, the first input of which is connected to the second output of the alphanumeric keyboard 3 , the first and second outputs of the demultiplexer 8 are connected respectively to the first and second inputs of the accumulating register 9, the third to the second input of the RS flip-flop 11, the fourth and fifth are connected respectively to the first and second inputs of the accumulating register 10, above the one with the third input of the electronic memory 2 read-write, the fourth output of which is connected to the input Zero of the accumulating register 10, the input Zero of the accumulating register .9 is connected to the third output of the alphanumeric keyboard 3, the outputs of the accumulating registers 9 and 10 are connected respectively to the first and the second inputs of the comparator 5.

The elements of the conversion unit 7 are connected as follows. The first inputs of the circuits 20,21,22.1-22.K and 23.1-23.R are connected to the outputs of the corresponding registers 24.25, 26.1-26.K and 27.1-27.R, the first inputs of group 28 of the N elements And through the corresponding elements of the group 48 of the N delay elements connected to the input 50 of the block and the second inputs of the circuits 20,21,22.1-22, K comparison, the second inputs of the group 28 of the N elements And connected to the output of the element AND NOT 35, and the outputs with information input buffer register 29 and the input element OR 37, the output of which is connected to the counting input of the counter 30 with the decoder and through the element 43

delays with the first input of the element 33, the first and second outputs of the counter 30 with the decoder are connected respectively to the first inputs of the trigger 31 and 32, the second inputs of which are connected to the input Resetting the counter 30 with the decoder, the first input of the element IS 36 and through the element 44 delays - with the first input of the OR element 38 and the output of the OR element 39, the first input of the latter is connected to the output of the comparison circuit 20, the second through the element 45 for 1425588

Thus, the first output is a group of N outputs.

Electronic read / write memory 2 is intended for storing information contained in a microfiche label and has two operating modes: Write and Read. It can be performed using the following 1Q elements: a random access memory with a read and write control device whose information input is the first input of memory 2; the counter of the support - with the release of the buffer Buffer-15, which determines the cell number of the open register 29, and directly - of the operative memory, with the output of the comparison circuit 21, which is addressed; This is the output 53 of the block, the direct output of the RS flip-flop 31 is connected to the first input of the NE-35 element, the second 20 random access memory — whose input is connected to the output of the element in read mode (in the replacement mode OR 40, the inputs of which are connected to the synchronization pulses of a post with the outputs of a group of circuits 22.1-22, K comparison, the inverse output of the RS flip-flop 32 is connected to the second input of the 25 flip-flops to form signals And ment 33, the output of which is connected to read or write with the second input of the element OR 38, exit after it is connected to the Record input and through delay element 46 with the input Read buffer register 29, the outputs of which are connected to the inputs of the OR element 41, the second inputs of the comparison circuit group 23.1-23.R and the inputs of the group 49 of the N delay elements, the outputs of the group 40 of the N delay elements are the block output 51, the outputs of the group of circuits 23.1-23, R comparison are connected to the inputs of the OR element 42, the output of which is connected to the second input of the AND-NOT element 36, the output of the latter is connected to the first input of the AND 34 element, the second

clock generator to synchronize the process of addressing

they feed through the second input of memory 2 from the reading head 1 directly);

thirty

 35

40

into a memory management device; switching elements of type AND and OR to send signals from a clock generator (in Read mode) or synchronizing pulses (received at the second input of memory 2 in Record mode) to the add-on counter of a demultiplexer dividing information from the random access memory on two channels: word transmission and coordinate transmission (respectively, the first and second outputs of the demultiplexer, the first output of the demultiplexer is the third output of memory 2); a demultiplexer dividing the coordinate information into the two last lean channels, X coordinates and Y coordinates (the outputs of this demultiplexer are the first and second outputs of memory 2); the control groups of the demultiplexer elements (a counter with a decoder, triggers, the switching elements of which are connected via the delay element 47 to the output of the OR element 41, and the output is the output 52 of the block.

The reading head -1, for example, consists of N + 1 optoelectronic sensors, in which photodiodes can be used. These sensors are pre45

into a memory management device; switching elements of type AND and OR to send signals from a clock generator (in Read mode) or synchronizing pulses (received at the second input of memory 2 in Record mode) to the add-on counter of a demultiplexer dividing information from the random access memory on two channels: word transmission and coordinate transmission (respectively, the first and second outputs of the demultiplexer, the first output of the demultiplexer is the third output of memory 2); a demultiplexer dividing the coordinate information into the two last lean channels, X coordinates and Y coordinates (the outputs of this demultiplexer are the first and second outputs of memory 2); control groups for the operation of demultiplexer elements (a counter with a decoder, triggers, switching elements are intended for simultaneous (parallels AND and OR), with which through the quadruple). reading N bits code memory output zero signal

is input to the Zero accumulating register 10 and to which, via the fourth input of memory 2, the output from S5 is returned from the output of the comparator 5.

 In the scheme for constructing the electronic memory 2 read-write (FIG. 3), the operational storage memory is indicated.

characters and strokes of the sync track, located, corresponding to the N-1, N-1 tracks of the microfiche label,

In this case, the codes of symbols generated in the electrical signals go to the first, and the synchronizing pulses go to the second outputs of the head.

Electronic read / write memory 2 is intended for storing information contained in a microfiche label and has two operating modes: Write and Read. It can be performed using the following elements: a random access memory with a read and write control device, and the formation input of which is the first memory input 2; an address counter that identifies the cell number of the RAM that is being accessed; read-only memory (in write mode, trigger clock pulses to form read or write signals

clock generator to synchronize the process of addressing

Electronic read / write memory 2 is intended for storing information contained in a microfiche label and has two operating modes: Write and Read. It can be performed using the following elements: a random access memory with a read and write control device whose information input is the first input of memory 2; an address counter that identifies the cell number of the RAM that is being accessed; read-only memory (in write mode, trigger clock pulses to form read or write signals

they feed through the second input of memory 2 from the reading head 1 directly);

Electronic read / write memory 2 is intended for storing information contained in a microfiche label and has two operating modes: Write and Read. It can be performed using the following elements: a random access memory with a read and write control device whose information input is the first input of memory 2; an address counter that identifies the cell number of the RAM that is being accessed; read-only memory (in write mode, trigger clock pulses to form read or write signals

into a memory management device; switching elements of type AND and OR to send signals from a clock generator (in Read mode) or synchronizing pulses (received at the second input of memory 2 in Record mode) to the add-on counter of a demultiplexer dividing information from the random access memory on two channels: word transmission and coordinate transmission (respectively, the first and second outputs of the demultiplexer, the first output of the demultiplexer is the third output of memory 2); a demultiplexer dividing the coordinate information into the two last lean channels, X coordinates and Y coordinates (the outputs of this demultiplexer are the first and second outputs of memory 2); the group of control elements of the demultiplexer elements (the counter with the decoder, the triggers, the switching elements AND and OR), with which through the fourth memory output the zero signal

device 5A with control device, demultiplexers 55 and 56, counter 57 addresses, generator 58 clock pulses, RS-triggers 59 and 60, elements OR 61-66, elements AND 67-70, counter 71 with a decoder, RS-triggers 72 and 73 , the first input 74 representing a group of N inputs, the second, third and fourth inputs 75-77, respectively, the first, second and third outputs 78-80 of memory 2, respectively, each of which is a group of N outputs, even yyrty output 81 memory 2,

The first output of the counter 71 with the decoder corresponds to a number equal to the number of characters of the code of the X coordinate, and the second output corresponds to the number of characters of the code of the coordinate Y.

The alphanumeric keyboard 3 is intended for the consumer to enter the search prescription information into the device by a character. One type of electromechanical keyboard can be used as an alphanumeric keyboard.

Encoder 4 is designed to convert electrical impulses; The ows, coming from the alphanumeric keyboard 3, into binary-coded signals, corresponding to the received N-bit character recording code in the device. Encoder 4 is an encoder and can be implemented using well-known encoder schemes used in computer input devices. The output of encoder 4 is a group of N outputs that serve to transmit all the code bits of each character in parallel.

Comparator 5 is designed to compare search prescription codes and search patterns and generate a match signal at its output. The comparator has two inputs, to which comparable codes are applied. In addition, each input is a group of inputs, where M is the maximum possible number of characters in a search prescription or search pattern, N is the code length of one character. The hardware implementation can be parallel-connected comparison circuits, for example K 555 SP1 chips, the outputs of which are combined using elements I.

55886

Multiplexer 6 performs the function of a switch having two information (first and second), two control (third and fourth) inputs and one output. The first and second inputs and output are groups of N inputs and outputs, respectively. Multiplexer 6 can be performed

0 according to the linear multiplexer scheme with direct input control.

Demultiplexer B performs the inverse function of multiplexer 6. With its fourth and fifth

The f inputs, which are control, connect the first, second, and third inputs to either the first, second, and third, or to the fourth, fifth, and sixth outputs, respectively. First entrance

The first and fourth outputs of the demultiplexer 8 are groups of N inputs and outputs, respectively, Demultiplexer 8 can be implemented, for example, according to the demultiplexer circuit with direct input control. one

Registers accumulating 9 and 10 are designed to store the codes of the search prescription 30 words and the search image, converted in block 7, respectively. Each of them can be executed, for example, in the form of a matrix of N static M-bit shift registers with control circuits.

recording and zeroing, hardware

These shift registers can be implemented on the basis of synchronous triggers. Serial registers manufactured in microminiature versions, for example, K 155 IR1, can be used.

In each of the N registers, recording is performed sequentially, and in the same-named bits of all registers, in parallel. The first inputs of the accumulation registers 9 and 10 are groups of N inputs and are information inputs of the registers. Information is recorded under the influence of recording signals arriving at the second inputs of registers.

9 and 10. The output of each of registers 9 and 10 is a group of

M n outlets.

Devices 14 and 15. Coordinate memories are memory registers, for example, parallel writing and reading, and are used to temporarily store the X and Y coordinate codes of a microfiche frame.

The following circuits 18 and 19 are designed to set the microfiche in position to read the desired frame. The diagrams are identical, and each consists, for example, of a differential amplifier of a body, a serpotentiometer, and a DC motor.

Static registers 24,25,26.1t 26, K, 27.1-27.R of conversion unit 7 are intended for long-term storage of N-bit codes recorded in them. Each of these is an N-bit parallel read register. These registers can be executed, for example, on switches or buttons, through which potentials corresponding to the required codes are supplied to the outputs of the registers.

Each of the circuits 20,21,22.1-22.K, 23.1-23.R of the comparison unit of the conversion unit 7 is intended for the comparison of two N-bit codes and the generation, in case of their coincidence, of a single output signal. Instrumentally, these comparison circuits can be implemented on the same elements as the comparator 5.

The buffer register 29 is intended for the temporary storage of bit codes. It represents N parallel two-digit shift registers with control circuits, i.e. similar to accumulating registers 9 and 10 when, but additionally has a read control circuit.

The decoder counter 30 is designed to count the number of 29 characters dropping on the buffer register. The counter 30 with the decoder myset be performed, for example, on the chips 555 IE 14.

In the counter 30 with the decoder involved two outputs. At the first output, the signal appears when the number Sj is written to the counter 30 at the second output, when the number L is written.

The delay elements 43-47 and a group of 48 of the N delay elements are designed to provide the required sequence of triggering of individual elements of block 7. Standard delay elements can be used as them.

The delay time of element 43 (T5,4i is chosen to provide

The simultaneous arrival of signals at both inputs of elements And 33, i.e.

t t 4-T

  Sp 30 1-1

where and T, p is the signal propagation delay time, respectively, in the counter 30 and the RS flip-flop 32.

The delay time of the element 44 (13.4 is chosen for reasons of reliability of the operation of the counter 30 and the RS-flip-flops 31 and 32 under the influence of a pulse preceding the counter-zeroing pulse. In addition, T must be such that

five

0

five

0

five

0

five

the simultaneous arrival of signals at the first and second inputs of the element AND-NO 36.

The delay element 47 is necessary to account for the extremity of the signal propagation time in the elements 41,23.1- 23.R, 42 and 36. The delay time of the element 47 () is chosen from the condition

 T, p 2}, p4g, where T, p, eb are the signal propagation delay times, respectively, in elements 41.23,42 and 36.

The delay times of elements 45 and 46 (T 5 and T, qg) are selected in order to ensure the following sequence of operation of register 29: Write, Read, Zero. And

T, 44 -T 4 T, 5.

A group 48 of N delay elements is necessary to ensure the following condition: upon arrival at the input of block 7 of the next character code, a signal to the first inputs of group 28 of N elements must be applied at the same time that the enable signal is removed from the second inputs of the group 28, if it is due to the algorithm. In other words, with the help of a group of 48 elements, we learn the presence of the time of signal propagation delays in elements 22.1 ,, 40 and 35, i.e.

five

0

.; i3.-i З p40 35

where t

9 8

9r2g

Ercho

the delay time of each element from the group of elements 48;

the propagation delay time of the signal in one of the elements 22.1-22.K; signal propagation delay time in the element OR 40;

p 35

the propagation delay time of the signal in the NAND 33 element.

At the expense of the group 49 of the N delay elements, the correctness and reliability of the operation of the other units proposed by the device, primarily registers 9 and 10, is ensured. The delay times of each element of group 49 () are equal to each other and are selected on the basis of the need to provide or simultaneous arrival of signals at outputs 51 and 52

records The contents of the microfiche label are recorded in memory 2.

To implement the second stage of operation, from the second output of the keyboard 3, a signal is supplied to the first input of the RS flip-flop 11 by means of which the multiplexer 6 and the demultiplexer 8 are set to one of two possible states, namely the corresponding search prescription reception. This state corresponds to the presence of single signals at the third and fourth inputs of elements 6 and 8, respectively.

 Block 7, or a simultaneous receipt, with responsibility. At the same time multiplexer 6

51 and withdrawal from exit 52,

 output signal; allowing signal i.e.

Tc) y, T, rge + T ,, p 36 + T, p j + T3, 7

The device works as follows:

In the initial position, all elements

; memory devices are in zero state, over. the exception of static registers 24,25,

26.1-26.K, 27.1-27.R of block 7 conversion; call. The first character of the word termination symbol is entered into the register 24, the end of the search-end character code is entered into the register j 25. image, coinciding with the code of the search prescription, in re-; 26.1-26.K are codes of uninformative symbols, for example, vowel letters of the alphabet, registers 27.1-27 .R are codes of other symbols used in words when forming the ending

The operation of the device is divided into the following steps, of which the third is performed after the first two:

1. Record the contents of the microfiche label in memory 2,

2. Input and coding search prescriptions.

3. Search for the required microfiche frame

and its installation. I

At the first stage, the memory 2 is set to the recording mode, and using the reading head 1, information is retrieved from the microfiche label, the conversion of the optically encoded information into electrical signals. At the same time, from the first output of head 1 to the first input of memory 2, the codes of search patterns are received, and from the second output of head 1 to the second input of memory 2 - synchronizing pulses

0

five

0

five

switches its first input with its output, and the demultiplexer 8 switches its first, second and third inputs to its first, second and third outputs, respectively. Next, the search prescription is entered using the keyboard 3. At the same time, the characters that make up the search prescription are fed from the first output of the keyboard 3 to the input of the encoder 4, in which they are represented as an N-bit binary code, exactly the same as that used for encoding information in the microfiche label. This code is fed through multiplexer 6 to the input of conversion unit 7 -. This unit is a central part of the present invention, therefore we will give a detailed description of it.

In block 7, the individual words of a search prescription are converted to such a form, which in most cases provides a single form of representation of words having different grammatical records. This implements the following word symbol processing algorithm. The word is divided into two parts: the first part contains the first S characters of the word, and the second contains all subsequent ones. The first part of the word during the conversion is retained unchanged. From the second part of the word, characters whose codes are written in static registers 26.1-26K are deleted. The stored characters of the word are located close to each other so that there are no spaces left in the place of the deleted characters. The number of saved characters is counted. If this number has reached the value of L, then all subsequent characters of the word are discarded.

The last character of the saved part of the word is analyzed. If he is

0

five

with one of the characters written to static registers 27.1-27, R, it is also discarded.

The order of operation of unit 7 is as follows. The impulses of the code of the next character of the word from the input of the block go to the second inputs of the comparison circuits 20 and 21 and the group of circuits 22,1t22, K comparison. A single signal is generated at the output of circuit 20 only if the received symbol is a word end symbol, since the word end code is written to register 24. Similarly, at the output of scheme 21, in terms of one word in

A single signal if the received symbol is an end symbol of a search instruction or a search pattern. At the output, the OR 40 element combining the outputs of the 22.1-22 K circuits produces a single signal only when the next character is a vowel. The passage of the next character code pulses through a group of 28 elements AND is controlled by a signal from the output of the element IS-NOT 35. According to the logic of this element, a zero closing signal is possible at its output only if there are single signals at both its outputs. This is possible only when a counter equal to or greater than S is written in the counter 30 with a decoder (the counter contents coincides with the number of characters passed through the group of 28 AND elements), and the received symbol is a vowel.

Thus, a group of 28 elements And cannot pass only codes of vowels, which are S + 1, S + 2 and t, d, in the order of the word. The 28 elements passing through a group of elements AND the pulses of the code of the next character are combined by the element OR 37, the output of which is connected to the counter input of the counter 30 with a decoder. Thus, the number written in the counter 30 corresponds to the number of characters of the word that passed through the group of 28 elements AND, the single signal at the first output of counter 30 with the decoder is generated only if it contains a number equal to S, and at the second output if it contains a number equal to L, These signals are memorized respectively by RS flip-flops 31 and 32, The pulse from the output of the element OR 37 is also used

to write the next passed group of 28 elements AND the character to the register 29, while passing this pulse to the input Writing the register 29 and through the input delay element 46 Reading the same register is possible only if the number in the counter is 30 less than L (only in this In the case of the inverse output of the trigger 32, there is a single signal that permits the passage of a pulse from the output of the element OR 37 through the element (33), Thus

five

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five

the register 29 is written no more than L of its characters. With the arrival of the character of the end of the word or the character of the end of the search prescription (search pattern), the counter 30 is zeroed by the delayed signal from the output of the IDN element 39, RS-triggers 31 and 32 are also set to zero, Pulses the character codes of the word end or the end of the search instruction (search image) pass through a group of 28 AND elements, since the second input of the AND-HE element 35 at this time contains a zero signal. The codes of these characters are also recorded in the buffer register 29 by a pulse from the output of the element OR 39, arriving at the first input of the element OR 38. In the register 29, the code of the next received character is written and transferred to the output bits of the previously received character, which is read by the pulse from the output element 46.

The symbol code read from register 29 goes through a group 49 of N delay elements to the output 51 of block 7 and directly to the second inputs of circuits 23,1-23, R comparison, while the output of the OR 41 element is pulsed subsequent elements of the device. The delay effect in register 29 of a prefix character is used to make the decision to save

0 or exclusion of the last character in the remaining part of the word, In particular, with the arrival of the word ending character at the output of the element. OR 39 a single signal appears that goes through element 44 to the first input of the element IS-NOT 36, If at the same time its second input receives a signal from the output of the element OR 42 (this situation takes place if

there was a comparison in one of the circuits 23.1-23.R), at the output of the AND-NE element 36 a zero signal is generated, which prohibits the passage of a write pulse from the output of the OR 41 element through the delay elements 47 and AND 34 to the output 52 of block 7. Otherwise x signal from the output of the element OR 41 passes through the element AND 34 and arrives at the output 52 of block 7 .. This corresponds to one of two cases; the next character received at the input of block 7 is not a word ending symbol (zero signal at the first input of the AND-NOT element 36); the next character is the word end character, but the previous character, which is detained in the register 29, is not compared with any of the characters written in. registers 27-1.-27.R (zero signal at the second input of the element AND-NO 36).

With the arrival of the symbol of the search image (search instruction), a coincidence signal is produced. At the output of the circuit 21. This signal arrives at the output 53 of block 7, and also through the delay element 45 - at the input

 Reset register 29. Additionally.

this signal, having passed through the elements OR 39, delays 44, zeroed the contents of the counter 30 and sets the triggers 31 and 32 to the zero state. Thus, after the arrival of the symbol of the search prescription (search image), block 7 is in its initial state and is prepared for processing the next position of information.

Consider the operation of subsequent blocks in the mode of i.vod and encoding the search prescription. In this mode, the signals from the outputs 51 and 53 of the block 7 are fed to the first, second and third outputs of the demultiplexer 8, respectively. Moreover, the signals from the outputs 51 and 52 go to the first and second inputs of the register 9, the contents of which are output to the first input of the comparator 5 The signal from the third output of the demultiplexer 8 is fed to the second input of the trigger 11, as a result of which it changes its state and switches the multiplexer 6 to transmit information to the output from its second input, and demultiplexer 8 to transfer information to its own tverty, fifth and sixth outputs. As a result, the device turns out to be

Q with n

five

0

five

0 5 0 55

prepared for the third stage of work - finding the right frame of microfiche.

At the third stage, memory 2 is translated into readings, and the search images recorded in it sequentially from its third output go to the second input of multiplex 6, are converted in block 7 similarly to the search prescription conversion entered in the search prescription input and coding mode. However, in this case, the signals from outputs 51-53 of block 7 are received, respectively, on the fourth, fifth and sixth outputs of demultiplexer 8. Consequently, the transformed search pattern is recorded in register 10 and fed to the second input of comparator 5 for comparison with the search prescription written earlier in register 9.

The signal from the sixth output of the demultiplexer 8 is fed to the third input of memory 2 and controls the output of the following X-coordinate codes for the search image on the microfiche of this image. Codes X and Y arrive at the first and second outputs of memory 2, respectively. After issuing the coordinate codes X and Y on the fourth output of memory 2, a signal is output to the Reset register 10. Thus, this register is prepared to receive the next search pattern coming from memory 2. If the code of the next search pattern matches the the search prescription code S recorded in register 9, at the output of comparator 5, a signal is generated that arrives at the first inputs of groups of elements And 12 and 13. By that cai-aiM, the X and Y coordinate codes are allowed to pass to the corresponding devices 14 and 15, storing the coordinates, Next, these codes are converted using digital-analog converters 16 and 17 to constant potentials. These potentials are fed to the following circuits 18 and 19, setting the microfiche in the reading position of the frame, the coordinates of which are recorded in devices 14 and 15. At the same time, the signal from the output of the comparator 5 is fed to the fourth input of memory 2 and interrupts the reading of information from memory 2 .

After resuming reading, it is possible to find the dah frame

microfiche corresponding to the established search prescription. To replace the search prescription, the read from memory 2 is stopped, and the third output of the keyboard 3 is given a register zero function 9. The elements of the read / write electronic memory 2 are next.

In the case of a recording signal in memory 2, this signal is transmitted by trigger 59 to the control device of the random access memory 54 and permits the passage of write clock pulses from the second memory input 75 through the AND 67 element to the OR 64 element and further to the counter 57 addresses. The information received at the first input 74 of memory 2 is recorded in the memory cell 54 in accordance with the addresses set in the counter 57. In case of a read signal transmitted by the trigger 60, the generator 57 receives pulses from the generator 58 and sends into the control device of the random access memory 54 clock pulses. In both cases, the counter 57 is pre-zeroed by signals from the output of element 70. The information is read first to the third output 80 of memory 2, since the reading signal through the element OR65 sets the trigger 72 to the zero state (simultaneously the trigger 73 is also set to the zero state). This state corresponds to the submission of information from the input of the demultiplexer 55 to its first output (it is also the third output 80 of memory 2). With the arrival of the search image termination signal from the output 6 of the demultiplexer 8 to the third input 76 of memory 2, the trigger 72 enters a different state, according to which the demultiplexer 55 switches the input information to its second output connected to the input of the demultiplexer 56. That the trigger 73 is at this point in the zero state, information from the multiplexer 56 is fed to the first output 78 of memory 2. This occurs as long as the X coordinate codes, the number of cycles, are needed for transmission X, is carried out by a counter 71 with a decoder, to which, in the coordinate transmission mode, the clock pulses are received through the AND 69 element. After counting the number of clock cycles required for transmitting the X coordinate, the first output of the counter 71 generates a signal that switches the information output in the demultiplexer 56 for its supply to the Y channel, i.e. to the second output 79 of memory 2; After passing the number of clock pulses sufficient to read the Y coordinate codes, the second output of the counter 71 receives a signal to switch the demultiplexers 55 and 56 to the initial state, resetting to the same signal with the same signal

counter 71. In the case of the arrival of a signal from the output of comparator 5 to the fourth input 77 of memory 2, the signal from the second output of counter 71 passes through AND 70 and interrupts the read by entering the input of OR 63.

Thus, in the proposed device, not the words of the search image and the search prescription are compared, but their transformations. These transformations preserve the most informative characters and combinations of words that carry a meaning, and exclude those characters that do not carry information and can be changed the transition from one grammatical form of using a word to another. Therefore, the proposed device, in contrast to the known one, allows one to find those frames whose search images have a grammatical form of writing words, different from the form of writing words in a search prescription.

Claims (1)

Invention Formula A device for reading microfiches with automatic frame setting, containing a reading head, an electronic read-write memory, the first and second inputs of which are connected respectively to the first and second outputs of the reading head, an alphanumeric keyboard, an encoder whose input is connected to the first output of the alphabetical numeric keypad, a comparator, two channels, each of which contains a series of N elements AND connected in series, a coordinate memory device, a D / A converter and the following inputs, the first inputs of the first and second groups of N elements I are connected to the output of the comparator, and the second inputs respectively to the first and second outputs of the electronic read-write memory, characterized in that 5 in order to improve the quality of searching for the required microfiche frames, it contains a conversion unit, a multiplexer, a multiplexer, two accumulating registers and the first RS flip-flop, the first input of the multiplexer is connected to the output of the encoder, and the second to the third output of the electronic read-write memory, the output of the mule The typelexer is connected to the input of the conversion unit, the first, second and third outputs of which are connected respectively to the first, second and third inputs of the demultiplexer, the fourth and fifth inputs of the demultiplexer are connected respectively to the third and fourth inputs of the multiplexer and the first and second outputs of the first RS trigger, The first input of which is connected to the second output of the alphanumeric keyboard, the first and second outputs of the demultiplexer are connected, respectively, with the first and second inputs of the first accumulating register, three s - to a second input of the first flip-flop RS-, fourth and fifth - respectively to the first and second inputs the second accumulating register, and the sixth — with the third electronic read-write memory input, the fourth output of which is connected to the Zeroing of the second accumulating register; the Zeroing of the first accumulating register is connected to the third output of the alphanumeric keyboard; the outputs of the first and second accumulating registers are connected to the first and second the second inputs of the comparator, the output of which is connected to the fourth input of the electronic read-write memory, wherein the conversion unit contains the first and second static registers, the group from K and a group of R static registers, the first and second comparison circuits, a group of K and a group of R comparison circuits, the first inputs of which are connected to the outputs of the corresponding static registers, the first and second groups of N delay elements, the third group of N elements AND whose first entrances are through the first group 0 5 Q five 5 0 5 A pu of N delay elements is connected to the input of the conversion unit and the second inputs of the first and second comparison circuits and a group of K comparison circuits, a buffer register, a counter with a decoder, a second and third RS flip-flops, six OR elements, two AND elements , two NAND elements, five delay elements, the second inputs of the third group of N elements AND connected to the output of the first NAND element, and outputs to the information input of the buffer register and to the inputs of the first OR element, the output of which is through the first element delays connected to the first in the first element and the second outputs of the counter with the decoder are connected to the first inputs of the second and third RS-flip-flops, respectively, the second inputs of which are connected to the input of the counter resetting the decoder, the first input of the second element And -NOT and through the second delay element - with the first input of the second OR element and the output of the third IZH element, the first input of the third OR element is connected to the output of the first comparison circuit, the second input through the third element is output - with output Resetting the buffer register, and directly with the output of the second comparison circuit j which is the third output of the conversion unit, the direct output of the second RS flip-flop is connected to the first input of the first NAND element, the second input of which is connected to the output of the fourth element OR, the inputs of the fourth element OR are connected to the outputs of a group of K comparison circuits, the inverse output of the third RS flip-flop is connected to the second input of the first element AND, the output of which is connected to the second input of the second element OR, the output of the second ele the OR input is connected to the Record input and through the third delay element with the input Read the buffer register, the outputs of which are connected to the inputs of the fifth OR element, the second inputs of the group from R. Comparison circuits and the inputs of the second group of N delay elements, the outputs of the second group of N elements delays are the first output of the conversion unit, the outputs of the group of R comparison circuits are connected to the inputs of the sixth OR element, the output is quick connected to the second input, the second delay element is connected to AND-NOT, the output of the second element AND-NEVER, the output of that element OR, and the output connected to the first input of the second ele- ral, the second output of the predominance block i, the second of which is through formation. -J 53 (Dtfff 2 52 7 o 75 o- Record about Ostan ( CviffntuS Q Poot. about  OcTOHoS. 6076 81 R & -077 65