SU1422329A1 - Single-phase frequency converter - Google Patents

Abstract

The invention relates to a converter technique. The goal is to increase reliability and improve overall dimensions. The device contains a bridge on the keys 1-4 AC, made on transistors 5-12. The output is turned on memory. capacitor 1.5. For the control of transistors 5-12, pulse sequences are formed which are formed by the control unit 16 in accordance with certain logical artifacts. 5 il. (L

Description

The invention relates to electrical engineering, in particular to static converters of alternating voltage of one frequency to alternating voltage of another frequency.

The aim of the invention is to increase the reliability and improve the mass-size indices by simplifying the power section, reducing the number of storage capacitors and reducing the distortion of the output voltage,

FIG. 1 shows the bridge circuit of the frequency converter in FIG. 2 - control unit; in fig. 3 is a diagram of a comparison device; in fig. 4 - voltage diagrams on the sectional elements of the circuit; FIG. 5 - zero converter circuit

:YOU..

A single-phase frequency converter contains a power part made by a bridge circuit on alternating current keys 1-4, based on transistors 5-12, which are connected to input pins 13 and 14, memory capacitor 15 at the output, control unit 16 and output pins 17 and 18. The control unit (Fig. 2) includes a first 19 pulse shaper with outputs 20-23 connected by an input to input voltages 13 and 14, a voltage source 24, at two output terminals 25 and 26 of which are formed signals U, and (U 1 comparing unit 27, connected in A second voltage source source 24, output voltages 17 and 18 with a Uftwx voltage, a second pulse generator 28, connected by an input to the first output 25 of a voltage source 24, and a logic unit that includes four two-input loops - a logical element OR 29-32 eight five-input logic elements And 33-40, and inputs associated with the outputs: 20-23 and 41-44 pulse shapers and the comparison unit, and the outputs - with the control inputs of the corresponding keys AC power part, and comparing controlling unit 27 is further connected to the first 21 and second 22 outputs and has a first shaper dopolnitelnsh output 45,

The control unit is additionally equipped with a third pulse shaper 46 with outputs 47 and 48, which are connected to the inputs of the logic unit (dual input; logic gates And 33-40).

The comparison (Fig. 3) contains amplitude comparators 49 and 50, the inputs of which are connected to the source 24 of the driving voltage and the output drivers 17 and 18 through the rectifier 51 and the matching transformer 52, the one-shot 53 and 54 whose inputs are connected to the first 21 and the second 22 outputs of the first driver 19 voltage pulses, two IK-flip-flops. 55 and 56, the inputs of which are connected to the positive power terminal, the inputs of the 1st outputs of the single-vibration 53 and 54, the inputs of K are with the outputs of the amplitude comparators 49 and 50, and their outputs are the output terminals 43-45 of the comparison unit, which are formed pulse sequences G3 (s), f (t), 5 (1)

The functional characteristic of a logical block, as well as its internal connections between logical elements (external with the control unit nodes) are defined by the following logical expressions:

f, (t) rf2 (t) .f / (t). f (t) .f, (t). -fj (t) + f (t) -f (t) .f (t) .f, (t).

f (t) rfi (t). f (t). f. (t). f7 (t).

.f (t) + f2 (t) .f (t): f (t). f (t).

€ 4 (t) J;

f, o (t) rf2 (t), f (t). f (t). f (t).

.f (t) + f2 (t) .f (t) .f (t) .f (t).

f3 (t) j;

f, (t) f (t). f (t). f ,, (t). f (t).

. (0 + f (t). F (t). F (t). F (t).

.

Ha FIG. 4 shows the input voltage 57 supplied to the input terminals 13 and 14, the voltage at the reference and 58 at the output 25 of the source 24 of the driving voltage, the pulses f (t) 59, the indicated rectified voltage f ,, (t), 60 , f ,, (t) 61, f (t) 62 control IU, I is fed to different inputs of amplitude comparators 49 and 50, on the other inputs of which output voltage 63 arrives (also higher than the direct voltage fU, (| K-Uj, l-, proportional to output voltage 63, g. K - proportionality coefficient. At the output of a fflithy day comparator, logical 1 is formed at I and. I | U, I, and at the output of amplitude to omparatora 50 - with lUjf .I trigger 55 provides output

laziness coming respectively to transistors 5, 12; 6, 11, 7, 10} 8, 9 j output voltage 63, generated at the output pins 17 and 18, voltage pulses 64 fy (t) at the first output 47 of the third voltage pulse generator 46, pulses f, (t) 65 , f | (t) 66, f2 (t) 67, f., (t 68 on the first 21, second 22, third 20, and fourth 23 terminals of the first driver 19 by them; indicated rectified voltage

IU, I goes to different inputs of amplitude comparators 49 and 50, the other inputs of which receive output voltage 63 (also higher voltage voltage fU, (| K-Uj, l-, proportional to output voltage 63, where .K proportionality factor). At the output of a fflithy-day comparator 48, logical 1 is formed at I and. I | U, I, and at the output of the amplitude comparator 50 - at lUjf .IK- a trigger 55 provides at the output

voltage pulses, pulses of the voltage- {5 gic 1 since the moment of transition of the input 69) on the first code 41 of the second shaper 28 pulses. N. FIG. Figure 5 shows the power part of a single-phase frequency converter, the use of which is especially expedient when the output voltage of small amplitude (ten volts) is formed. Frequency converter | Fig. 5) contains a storage capacitor 70, two key elements 71 and 25 72, on transistors 73-76, the first power electrodes of which are connected to the first (upper) plate of the storage capacitor 70, control unit 77, matching transformer 30, primary the winding of which is connected to the input terminals 79 and 80, is secondary to the second sylove electrodes of the key elements 71 and 72, the middle point of the secondary winding is to the second (lower) lining of the storage capacitor 70, and the output terminals 82 and 83 are connected to the storage plates condensation Ator 70. Control block 77 is similar. . Q control block 16 (Fig. 2 and 3).

voltage of 57 through zero to the moment of equality. This is achieved due to the formation of narrow voltage pulses with a single vibrator 53 along the leading edge of the pulse 67 and the amplitude comparator 49 at the moment of equality | U ((. IK-trigger rep 56 provides the output logic 1 from the moment of maximum input voltage 57 to the moment of equality Such a construction of the comparison block 27 allows to exclude a large number of commutations (there will be only two commutation of the key elements .1–4) at the half-period of the input voltage 57, which leads to an increase in the efficiency of the converter as a whole. 46 voltage pulses determine the time intervals where the accumulator capacitor 15 requires discharging, is connected to the output of the amplitude comparator 49 and generates 64 voltage pulses at the output, the leading edge of which is determined by the parameters of the load and the storage capacitor 15, and the slice coincides with the moment when the output voltage passes through zero. Decreasing the load or increasing the capacitance of the storage capacitor causes the leading edge of the voltage pulses 64 to shift to the left in the limit moment of maximum amplitude voltage of the input voltage 63. The simplest embodiment skheOdnofazny frequency converter (FIG. 1) works as follows.

An input voltage 58 arrives at the input of the first driver 19 for pulses, and pulse sequences 67, 65, 66, 68 are formed at its outputs 20-23. On you45

voltage of 57 through zero to the moment of equality. This is achieved by the formation of narrow voltage pulses with a single vibrator 53 along the leading edge of the pulse 67 and the amplitude comparator 49 at the time of equality | U ((. IK-trigger rep 56 provides a logical output 1 from the moment of maximum input voltage 57 to the moment of equality. Such a construction of the comparison block 27 allows to exclude a large number of switching (there will be only two switching of the key elements .1-4) on the half-period of the input voltage 57, which leads to an increase in the efficiency of the converter in the whole. Voltage pulses determine the time intervals where the discharge capacitor 15 requires, is connected to the output of the amplitude comparator 49 and generates 64 voltages at the output, the leading edge of which is determined by the parameters of the load and the storage capacitor 15 and the cutoff coincides with the moment when the output voltage passes through zero. Decreasing the load or increasing the capacitance of the storage capacitor causes the leading edge of the voltage pulses 64 to shift to the left in the limit cient maximum voltage amplitude of the input voltage 63. The simplest version scheme d-l H1rLLChCh:; pg1L U-J. ilpui- 1 CiHUUlJKl ± cll nclt1i WA.C -

In the course of 25, the driving voltage of the third driver 46 impulse is generated and supplied to the second driver 28 of voltage pulses, the voltage 69 at the first output 41 of which is formed, and the inverted voltage 66 f (t) at the second output 4.2. At the second output 26 of the driver voltage source 24, a rectified voltage 58 is formed.

co-voltage is based on a differentiating chain, which does not feel the narrow voltage pulses coming from the output of the amplitude coupling 49 in the time interval t, -

thirty

- t

k.2

and narrow failures

the output voltage of the amplitude comparator 49 in time intervals

1 from the moment of transition

voltage of 57 through zero to the moment of equality. This is achieved due to the formation of narrow voltage pulses with a single vibrator 53 along the leading edge of the pulse 67 and the amplitude comparator 49 at the moment of equality | U ((. IK-trigger rep 56 provides the output logic 1 from the moment of maximum input voltage 57 to the moment of equality Such a construction of the comparison block 27 allows to exclude a large number of commutations (there will be only two commutation of the key elements .1–4) at the half-period of the input voltage 57, which leads to an increase in the efficiency of the converter as a whole. 46 voltage pulses determine the time intervals where the accumulator capacitor 15 requires discharging, is connected to the output of the amplitude comparator 49 and generates 64 voltage pulses at the output, the leading edge of which is determined by the parameters of the load and the storage capacitor 15, and the slice coincides with the moment when the output voltage passes through zero. Decreasing the load or increasing the capacitance of the storage capacitor causes the leading edge of the voltage pulses 64 to shift to the left in the limit moment of maximum amplitude voltage of the input voltage 63. The simplest embodiment skheH1rLLChCh:; pg1L U-J. ilpui- 1 CiHUUlJKl ± cll nclt1i WA.C -

The third voltage pulse former 46 is based on a differentiating chain that does not feel the narrow voltage pulses coming from the output of the amplitude comparator 49 in the time interval t, -

thirty

- t

k.2

and narrow failures

the output voltage of the amplitude comparator 49 in time intervals

514223296

-to. -} о к.2 60 The pulses are divided by the moment of equality of the voltage, f (t) 59, incoming signals (11} (and | U, |, determined by comparing transistors 5 and 12 in the time interval of 27) output 43). Before: NO to - tj ,, are formed at the output

the first pivod logic

(element 33). At its inputs there arrive pulses 65 and 67 from the outputs of the first fornt of pulses 59 and 62 of the control; the first driver 19, pulses 69 s

neither in the time interval t, - tj and pulses 60 and 61 in the time interval (".2. 60 is determined by the moment of maximum output voltage 57 (imjnepBoro output 41 of the second shaping pulse 68), and their section is determined by 1n 28, inverted pulses. At the moment of equality of stresses 11b1 and

64 (64) from the second output 48 of the third u, l, determined by comparing the block of driver 46 and pulses with output 27 (output 44).

143 of the comparison unit 27. Impulses The power part of the control converter 59, which enters the intervals, is as follows. t time t. f tran-According 59 in the time interval

Eistors 5 and 12 form a control pulse fj (t) at the output of the te - t along the .de of the second pilot input. the transistors 5 and 12 of the AND 34 terminal. At its inputs, the inputs turn on at the time of the transition, impulses 68 and 66 from the outputs of the primary 20 voltage 57 through the zero. After to the voltage pulse generator, the instantaneous value of the extracted voltage t9j is 69 inverted pulses of the output voltage 63 of a given value 69) from the output 42 of the second formed (IU, /) defined by 4 28, and ffly 64 from the output 47 voltage of 58, on. exit 43

From the former 46 in, the pulses from 25 of the comparison block 27 appear to be lo. respiration unit 44 of the comparing unit 27. Vygic O, which provides a separate impulse sequence of control voltages from the transistor input logic elements of Isistor 5 and 12. From this point on, time 33 and 34 arrive at the two input bar until the load t the semi-OR element 29 and-on it de-energizes the storage capacitor 59 fj (t) 15 from the memory capacitor. At the time tf (mon-

5 | boards for transistors 5 and 12.. Control pulses 60, 0 (t) for tfansistors 6 and 11 are formed on the PSU of the logic elements AND 37 and 38. The pulses 60 of the control P in the time interval t, - tj are formed on the output of the PTIV of the logic element AND 37 due to feeds to its inputs of pulses 68 f2 (t), l 65 f (t), 69 fj- (t), 64 fj (t), for example, and from the output 44 f (t) of the comparison block 27. Pulses 60 control in the time interval tj -t 2 s at the output of the two input input logic element, AND 38. At the output of the two-input logical element OR 31. pulses 60 are formed, which are fed to the control electrodes of transistors 6 and 11. Pulses 61 "(t)

35

The transition point of the input voltage 57 through zero) control pulses 62 fg (t) are sent to turn on transis -. tori 8 and 9, the moment of shutdown of which is also determined by the moment of equality of the voltages I U} I and. Switching off these transistors is also provided by forming a logical O on the second output 43 of the comparing unit 27. In the time interval to - tjj; the control pulses 59 and 62 are sent only to transistors 5, 12 and 7, 8. In the time intervals t .l 30

- t

K.2

carried out

and 62 f (t) controls, respectively, for the transistors 7, 10 and 8, 9 are formed in a similar way (Fig. 2). The leading edge of the pulses 59 and 62 of the control in the time interval t, -tK. (

50

The charge of the storage capacitor 15 is from the primary network 13-14, and in the time intervals tgjj, n.Z 6ff, .. the discharge of the storage capacitor 15 occurs through the primary network. In the time intervals t - t,, z.k.d, the voltage Ugj on the capacitor 15 is not greater than the reference U, i.e. always, In time intervals t "(- t3 (,, t j -, ... for example - - - - -" .---, - y- .1

i-pulses 60 and 61 in the interval of time Ug on the capacitor 15 is not less

The name is determined by the moment of the given U, i.e. jujt. In the input voltage input 57 through the time interval - tj, pulses

zero (pulses 67), and their cut-off of control-60 and 61 controls receive the corresponding fornt of control pulses 59 and 62, and up to time t, the load receives power from the storage capacitor 15. At the time tf (mon-.

The transition point of the input voltage 57 through zero) control pulses 62 fg (t) are sent to turn on transis -. tori 8 and 9, the moment of shutdown of which is also determined by the moment of equality of the voltages I U} I and. Switching off these transistors is also provided by forming a logical O on the second output 43 of the comparing unit 27. In the time interval to - tjj; the control pulses 59 and 62 are sent only to transistors 5, 12 and 7, 8. In the time intervals t

K.l 30

- t

K.2

carried out

The charge of the storage capacitor 15 is from the primary network 13-14, and in the time intervals tgjj, n.Z 6ff, .. the discharge of the storage capacitor 15 occurs through the primary network. In the time intervals t - t,, z.k.d, the voltage Ugj on the capacitor 15 is not greater than the reference U, i.e. always, In time intervals t "(- t3 (,, t j -, ... for example

Ug on condenser 15 is not less

It is possible to transistors 6, 11 and 7, 10.

ti, + tiz

2

In the time interval

- t HM pulse 61 of the control enters trans-resistors 7 and 10, and its front coincides with the moment of maximum input voltage 57 (associated with pulses 63), and the cutoff coincides with the equal time | Ujl and. | Ut (determined by the Yu unit with the matching unit 27. The receipt of control pulses on the transistors 7 and 10 at the time of maximum input voltage 57 eliminates large differential currents in the capacitor circuit 15. 15

At the moment of time

ti2.it2i

The impulse 60p. of the voltage enters the transistors 6 and 11 and is taken off at the moment of equality of the voltage lUjI and iU I. In the interval,

At the time of -t30 (Fig. 4), the control terminals 60 and 61 are supplied only to transistors 7, 10 and 6, 11. The operation of the frequency converter in the interval tj, -tj gives a complete picture of its operation in general. The leading edge of the pulses 60 and 61 of the control, arriving at the transistors 7, 10 and 6, 11, in the time interval tjj, -t, coincides with the moment of zero crossing of the input voltage 57, and their cutoff coincides with the moment of equal voltage I I. The leading edge of the pulses 59 and 62 of the control coming to the transistors 5, 12 and 8, 9, in the time interval tK.z bo coincides with the maximum input input voltage 57, and their cutoff coincides with the moment of equality of the voltage and (.

A single-phase frequency converter (FIG. 5 is a second converter unit) operates as follows.

The same pulse sequences 59-62 are used to control the transistors 73-76. The pulses 59-62 of the control act accordingly on transistors 74, 73, 76, 75. This circuit, unlike the circuit (Fig. 1), has a matching transformer 78 and two key elements 71 and 72 on transistors 73-76. This frequency converter circuit is advisable to use when generating a small amplitude voltage (tens volts) at the output pins 82-83, when the serial connection of key signals performed on transistors and diodes significantly affects

Efficiency, reliability and the form of the output naprShsh1. Matching transformer 78 provides matching of input voltage of 57 (hundreds of volts) and travel voltage of 63 (ten volts). As can be seen, such a frequency converter as compared to the converter according to FIG. 1 has two times fewer key elements. With a positive voltage polarity at the beginning of the secondary winding, the control pulse 59 arrives at the moment the input voltage 57 passes through zero (time tjj) to the transistor 74, which is provided by-. The charge of the storage capacitor 70 is from the upper semi-winding. The moment of turning off the transistor 74 in the time interval to-t coincides with the moment of equality of the voltages and | U (which determines the comparison block 27. In the other half period of the input voltage 57, the control pulse 62 enters the transistor 75, while the front of the control pulse 62 coincides with the moment of transition of the input voltage through zero t /, and its cut - with the moment of equality of the voltages lUjI and iU, (. The control pulses 59 and 62 in the time interval to- arrive alternately at transistors 74 and 75 for podzark dki storage capacitor 70. In and In the time interval tj | - tj, the control pulses 61 and 60 are applied to transistors 76 and 73, with this volume the leading edges of the control pulses coincide with the maxima of the input voltage 57, and the cuts with the moments of equality of the voltages I U-jl and IU, 1. In the time interval tj. - the capacitor 70 is discharged through the secondary winding of the matching transformer 78. The control pulse arrival sequences 59-62 in the time intervals tj. In addition, they illustrate the operation of the frequency converter (Fig. 5).

Thus, the proposed frequency converters advantageously differ from the known ones with higher reliability, efficiency, less weight and overall dimensions due to the halving of the number of keys and storage capacitors. Frequency converters are especially effective when forming a low-frequency voltage at the output and with a large difference in the frequency of the input and output voltages.

Claims (1)

Invention Formula Single-phase frequency converter containing the power part in the form of at least four fully up. equal AC switches connected between the input and output gates, a storage capacitor, the first plate connected to the first output output of the converter, and a control unit that includes the first pulse driver connected to the input pins and formed at the output of the output pr. My and inverse pulse sequences f (t), f | (t), coinciding in frequency and phase with the input voltage, and sequences ),), the frequency of which pr-20 scans twice the frequency of the input voltage and coincides with it in phase, the source of the driving voltage, which is formed by the signals Uj and I Uj I generating the two outputs, the comparison unit, 25 inputs connected to the second output of the driving voltage source and the output pins with the voltage UBMX, which provide on the outputs the pulse sequences r, () and 30 f (t), the logical unit on which the second pulse generator is formed at UjI4 JK-UBb, and Shz / i I K-Ug, J, respectively connected by the input to the first output of the source of the voltage and providing the output direct and inverse pulse sequences fyCt) and f (t) coinciding in frequency and phase with a given voltage U,, as well as a logical block connected to the outputs of the pulse shaper and a comparing unit, and outputs - with the control inputs of the corresponding AC switches of the power unit, which is characterized in that, in order to increase reliability, improve the weight and dimensions, four AC switches are connected according to the bridge circuit, one diagonal of which forms the input and the other diagonal the output pins, the second lining of the storage capacitor is connected to the second output of the converter, the comparing unit is additionally connected to the first and. the second outputs of the first pulse generator and made the pulse sequence f (t) forming the third output, the logical unit on which is formed when I Uj II K. Ugu ,, I, the control unit is additionally equipped with a third pulse shaper, made to provide two pulses sequences f (t) and f (t), the logical units on which are formed, respectively, with lUjI K. и0 (, "| and lUgl i IK-UBM" |, whereby the logic unit is additionally connected with the outputs of the third pulse generator and is completeimplementing on their outputs pulse sequences fg (t) rf (t). i (t) .f (t) .f (t). .f (t) f (t) .f, (t) .f. (t) .f, (t) .. fg (t) ffjt) .f (t) .fj. (t) .f (t). .f (t) -t- f (t) .f (t) .f (t) .f (t). ); f (t) .rfi (t) .fi (t). . (t) .f (t). .f, (t) + f (t). f, (t). f (t). f., (t). ); f, / t) rf, (t). f (t). f (t). f (t). .f, (t). + f (t). f / (t). f (t). f, (t) r fjCt). Cltd . , fcj and / -dg -if Ljp F w t f. . 25 „4 / IpLLii n.tg