SU1417040A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing and can be used as a buffer storage device in information collection and processing systems operating in a mode with preliminary accumulation of a data block, in particular for recording information on a magnetic tape using locked data records. The aim of the invention is to reduce the power consumed by the device and to expand the field of application of the device due to the provision of reading in the last-entered-first-out mode. The device operates in the recording mode and in two modes of Mteeni: reading with the discipline of service first entered — first out, reading with the discipline of service last — entered first. The reduction in power consumption is due to the fact that the supply voltage is connected to the key, controlled by triggers, only to those of the memory blocks that are currently involved in data storage. The recording of information begins with the first memory block, which is connected to the supply voltage at the initial setting on the inputs, and is performed sequentially in subsequent memory blocks. When reading, the decoder switches off through the keys those memory blocks to which no information has been written, which does not lead to distortion or loss of information in the reading. 1 il. with% (L 4

Description

The invention relates to computing and can be used as a buffer storage device in data acquisition and processing systems operating in a mode with a preliminary accumulation of a data block, in particular, for recording information on a magnetic tape using locked data records.

The aim of the invention is to reduce the power consumed by the device and to expand the field of application of the device by providing readings in the last entered mode — first out.

The drawing shows the functional scheme of the device.

The device contains blocks 1 1 wpa-20 him the front of the signal at the input 16,

25

thirty

Mits with information inputs 2 and outputs 3, keys, voltage input 5, triggers, a group of elements OR the first 8 and second 9 inputs of the installation, the first block 10 of comparison with a constant, with a pair of three groups of elements And 11,,, the first 14 and second 15 inputs of the mode control, the input 16 of the gating, the first 17 and the second 18 elements of HE, s; the first for the fifth elements are And 19-23, the third input 24 of the installation, the second block 25 is compared with the constant, the first to the third shapers 26 are 28 pulses, the first to the third depressors 29-31, the counter 32 addresses, the counter 33 memory cells These are the first to third elements OR 34-36, delay element 37, ILIT-NOT 38, exit 39 of the end of reading, and exit 40 of the end of the record.

The number n + 1 of the counter bits 32 addresses is equal to the number of memory cells of all blocks, and determines the information capacity of the device. The number of sections of the counter count of 32 memory cells is one bit higher (:: the counter has 32 addresses. Each of the blocks contains N memory cells.

35

40

passing through elements AND 22 and OR 34, the contents of counters 32 and 33 are modified, i.e. a unit is added to their contents. The following information packets of input 2 are recorded in the same way. During the recording in block 1 of the Nth informational row, where is a constant, the output of block 10 is a signal matching the address with the constant N, and the output of the decoder 30 appears which is through the indoor element AND 1 1; set trigger 6 to single state. The high level of the signal at the output of trigger 6 supplies the key voltage to block 1 of the power supply via a switch. The value of N is chosen such that

,

t max

the maximum frequency of the signal set at 16; t is the time taken to

inclusion of the following ka 1;

NO is the number of cells in the memory block.

where f

Alax

The first service entered the first type of service (FIFO), the service discipline reading last entered the first time (LIFO). The recording mode is set to a high level at the input 14. The high signal level at the output of flip-flop 6 allows the passage through | Sluch. 4, i of the power supply from the input 5 to the memory block 1. Low levels of signals at the outputs of the remaining triggers block the passage of the supply voltage to the blocks

With the arrival of the information sprinkling on the inputs 2, accompanied by a signal at the input 16 acting on the decoder 29, data is recorded in the first cell of the block 1. The falling edge of the signal at the input 16,

passing through elements AND 22 and OR 34, the contents of counters 32 and 33 are modified, i.e. a unit is added to their contents. The recording of subsequent information packets from input 2 is similar. During writing to the N block of information block 1, where the constant, the output of block 10 is the address matching signal with the constant N, and the output of the decoder 30 is a signal that through the open element AND 1 1; sets trigger 6 to one. The high level of the signal at the output of the trigger 6 supplies via the switch the supply voltage to the memory block 1. The value of N is chosen such that

,

t max

the maximum frequency of the input signal at input 16; t is the time taken to

the inclusion of the next block 1;

NO is the number of cells in memory block 1.

where f

Alax

The device works as follows.

By starting the operation with a signal at input 24, the counters 32 and 33 and the 6p-6 triggers are set to zero with a signal

About inlet 9.

The trigger 6 is set to one by signal 1 at input 8.

The device has three modes of operation: recording mode, reading mode

Similarly, all subsequent blocks 1– 1 .. are put into operation and informational records are written into them.

W link

blocks 1, -1 .. are defined as decrypt1 / w

rum 30, the signals from the outputs of which are alternately through the open elements AND P, starting with the second one (Triggers are set to one state).

314

The duration of the recording mode is determined by the presence of a high level signal at input 14. The moment of filling the information capacitance; the device is recorded as high level at the output 40.

The FIFO service discipline reading mode is set by setting the low level of the signal at input 14 and the high level of the signal at input 15. By setting this reading mode to a positive differential signal at the output of the I 19 element, the driver 26 generates a signal that through the OR 35 element sets the counter 32 zero state. At the same time, by a negative signal drop at input 14, the driver 27 generates a signal that gates the decoder 31, the output signals of which provide the disconnection of those blocks to which the supply voltage is applied, but the data were not recorded. The inputs 14 of the blocks 1 are supplied with a low signal level, which sets the reading mode for them. When performing a read operation, an input request is submitted to input 16, which, acting on the decoder 29, provides reading information 3 from the first cell of block 1. . At the end of the reading, the back, front of the signal at input 16, passing AND 23 and OR 34 elements, adds one to the contents of counter 32, and a unit subtracts from the output of OR 36 element from counter 33. The reading of subsequent information parcels from the device is similar. After reading the data from the first block 1 is finished and reading from the next, for example block 1, begins, the signal at the second output of the decoder 29 through the open first element And 12 trigger b is set to the zero state, which leads to the disconnection of the supply voltage from block 1. Similarly, after reading the information from each of the subsequent blocks C-1d, the latter are disconnected from input 5. When reading the information at the moment when the contents of counter 33 are Nj, -N, which is fixed by block 25 the output signal of the afterbirth it establishes through. Element And 11. Trigger 6 in the Single state, thereby preparing Block 1i for

write data. Upon completion of the data reading, which is recorded by the appearance of a high level signal at output 39, shaper 28 is triggered, the output signal of which through the elements of OR 7 group confirms the zero state of the flip-flops.

The readout mode with the LIFO service discipline at the end of the write mode is set by setting the signal to low on inputs 14 and 15. At the same time, the output signal from shaper 27 gates decoder 31 and disconnects from input 5 the power of those blocks that are not recorded. When the operation is performed, the read request arrives at the input 16, which, acting on the decoder 29, reads the outputs 3 of the data from the last completed block in the write mode, and the address of which is contained in the counter 32. Upon completion of the reading

the falling edge of the input 16,. passing through the elements AND 21 and OR 36, one is subtracted from the contents of the counters 32 and 33. The reading of subsequent information packages is done in a similar way. After reading the data from the 1st block (where Ki iM) of the block is completed and reading from (il) -ro block 1 begins, the signal on (il) -M output of the decoder 29 through the open i-th element AND 13 and the OR element 7, the i-th trigger 6 is set to the zero state, which disconnects the i-th block 1 from the power input 5. Similarly, after the reading of information from all the blocks is completed, all of them will be disconnected from the power input 5. After the last informational dressing from the first block 1 is read, a signal appears at the output of the counter 32, which through element 37 for the holder and the element OR 35 enters the installation input in О of the counter 32, preparing it for the recording mode

data.

Claims (1)

Invention Formula A buffer memory containing M (where M is an integer) of memory blocks, (n + 1) -digit address counter, where (n + 1) is an integer, l-log, M), the first element is And, first and second decoders, H keys, M the triggers, the first and second groups of elements And, the first and second elements are NOT and the first unit of comparison with the constant, the information inputs and outputs of the memory blocks, respectively, but combined and being information inputs of the device, the outputs of the low-order bits of the address counter are connected to the inputs from the first to the fifth first comparison block with the constant and address inputs of the memory blocks whose write-read resolution inputs are connected to the same-decoder outputs of the same name, whose strobe input It is connected to the gating input of the first comparison unit with a constant and is the device gating input, the information inputs of the first and second decoders are connected jK to outputs 1: the higher bits of the address counter, the output of the first comparison unit to the constant is connected to the input: gating the second decoder, the outputs of which are connected to the first inputs of elements AND from the second to the M-th first group, the power input of each memory unit is connected to the output of the key of the same name, the control input of which is connected to the output of one The first trigger of the first trigger is connected to the output of the first element of the third group, the first inputs of the elements of And with the M-th of the second group are connected respectively to the outputs of the M- the first through the first decoder, the voltage supply inputs of the keys are combined and are the input voltage of the device power supply, the information input of the first trigger is the first installation input of the device, the information inputs of the second to M flip-flops Are connected and are the second installation input of the device, the trigger synchronization inputs are combined and are the third installation input of the device, characterized in that, in order to reduce the power consumed by the device and expand the area of application of the device by providing a read in the last entered mode, the first , a second comparison block with a constant, a third depffrator, (n + 1 + 1) -discharge 4170406 the memory cell counter, the third group of elements AND, the first to the third pulse shapers, the first to the fifth element AND, the first to the third elements IL, the delay element, the element OR NOT and the group of elements OR, and the inputs of the installation O of triggers from second to mth are connected to you 10 moves of elements OR groups, the first inputs of which are connected to the outputs of the third decoder, the information inputs of which are connected to the outputs of the 1 most significant bits of the volume counter 15 memory, the inputs of the first group of the element OR-NOT and the inputs of the first group of the second block of comparison with a constant, the inputs of the second group of which and the inputs of the second group of the element OR-NOT 20 are connected to the outputs of the lower bits of the memory volume counter, the reset input of which is connected to the trigger inputs of the flip-flops and the first input of the second OR element, the output of which is connected to the reset input of the address counter, the loan output of which is connected to the second input of the second element OR, the third 30 whose input is connected to the output of the first pulse generator, whose input is connected to the output of the first element I, the first input of the first element I of the first group, the second inputs of elements I from the first to () -th second group and the first input of the fifth element I, whose output connected to the first input of the first element OR and the first input of the third element 11PI, the output of which is connected to the counting input of the counter of the memory cells, the overflow output and the direct counting input of which are connected respectively to the input of the element OR NOT Fourth Go 40 And the second input of the first OR element, the output of which is connected to the input of the direct count of the address counter, whose countdown input and the second input of the third OR element are connected to the output of the third AND element, the first input of which is connected to the output of the second AND element the first inputs of elements AND the third group. The second inputs of which are connected to the outputs from the first through (M-1) -th first decoder, the gate input of the third decoder is connected to the output of the second pulse driver, the gate input: the second comparing unit 714 with the constant, the first input of the fourth element And, the second inputs of the third and fifth elements And connected to the input of the gating of the first decoder, the output of the second comparison unit with the constant connected to the second input of the first element AND of the first group, the second inputs of the elements OR of the group connected to the outputs of the elements AND from the second to the M-th of the second group, the outputs of the elements AND the third group are connected to the third inputs of the elements OR of the group, the fourth inputs of which are connected to the output of the third pulse generator, the input of which is connected to the output dy element Hilti NOR first inputs of first and second AND gates connected to the output element of the first NOR input of which, input vtoSostavitel T.Zaytseva Editor E.Kopcha Tehred A.Kravchuk Corrector Bout ha Order 4070/49 Circulation 590 VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 70408 the second pulse generator, the second input of the fourth element I, the second inputs of the elements AND from the second to the Mth first group, the second input of the Mth element AND of the second group, and the write-read inputs of the memory blocks are combined and are the first input for controlling the operating mode of the device second entrance 0 of the second element AND is connected to the output of the second element NOT, the input of which and the second input of the first element AND are combined and are the second control input for operating the device, 15 the output of the reading end of which is the output of the element OR NOT, the output of the recording end of the device is output counter overflow memory cells. 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