SU1417004A1 - On-line memory addressing device - Google Patents

Abstract

The invention relates to a computational technique and can be used in a computer with random access memory, the volume of which is greater than the addressing area of operands in the instruction set. The purpose of the invention is to increase the speed of the device when accessing different memory blocks. The memory addressing device contains three registers, two decoders, four AND elements, an OR element, an NOT element, and a channel transmitter block. Improving the speed of the device is provided by automatic reprogramming of the addresses of the memory block numbers during the alternating access to different memory blocks. 1 il. with

Description

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The invention relates to a computer technique and can be used in a computer with RAM, the volume of which is larger than the address area of the operands in the instruction set.

The purpose of the invention is to increase the speed of the device. When accessing different blocks of memory,

The drawing shows the functional scheme of the device.

I The device consists of bus 1 address | a, bus 2 data bus. 3 controls, block 4 of program memory, decoder 5, elements 6 and 7, register 8, element 9 and decoder 10, block AND anal transmitters, element 12, NOT 13, element OR J4, registers 15 and 16, data memory block 17.

: Low order bits of bus 1 address tto- Are connected to lower bits of the address inputs of block 4 of program memory and blocks 17 of memory and decoder 5. High bits of bus 1 address are connected to the information inputs of register 15 and the inputs of the And 12 element whose output is connected to the inputs selection. ki register 16, decoder 10 and through the element NOT 13 to the input of the sample register 15 and the input of the block 4 of program memory. Data bus 2 is connected to the information inputs of registers 8 and J6, blocks 4 and 37 of memory, and outputs of the block JJ of channel transmitters.

The control bus 3 consists of several bits. The discharge input bus 3 is connected to one of the inputs of the element 9. 9. The discharge output of the bus 3 control NIN is connected to the inputs of the elements 6 and 7.

The input and output bits of the control bus 3 are connected respectively to the read and write inputs of the program memory block 4, memory blocks 17, as well as the inputs of the OR 14 element, the output of which is connected to the inputs of the sampling of registers 16 and 15.

The device works in the following way.

The device allows to dry up, addressing the memory cells by preprogramming it, i.e., indicating the memory block number and the page inside the block to be accessed. A look at the program memory block 4 is produced

without prior programming of the device.

The block number and the page number are stored in registers 8 and 16, respectively. These registers are selected by assigning conditional own numbers in the system of external computer devices using this addressing device. The number arrives at the address 1 bus to the decoder 5 which identifies its own register number 8 or .16 and allows the write pulse passed through the AND 6 or 7 element received by the control bus output 3 line to the register entry 8 or 16. This a pulse is recorded, respectively, of the incoming, and the data on the bus 2 data block number in the register 8 or page number in the register 16. The selection of the corresponding memory block 17 is performed using the decoder 10.

A block of 11 channel transmitters with a three-stage output, a controllable signal. The input sends information to the data bus from register B, if necessary, to monitor its state.

Multistable registers 15 and 16 are included in this way — that when the sampling signals are fed to their sampling inputs, register 15 permits the passage of the signal from the information inputs to the outputs, and the information recorded in it earlier arrives at the output of register 16.

The number of pages in each of the memory blocks is determined by the number of high-order bits of 1 address assigned to register 15 and element 12. For example, if two bits are connected to them, then each of the blocks of 17 memory is divided into four pages.

The device works as follows.

LR and meer. Let each of the 17 memory blocks has 64 K bytes of memory and is broken into; 4 pages:. The memory, t, e, is used for addressing the page by two high-order address bits. Block 4 of program memory has 48 K bytes of memory. The addressing field is conventionally divided into two zones: the first is 48 K bytes, the second is the remaining V 6 K b ai.

If the address of the required IP is located within the nepBoii zone, i.e. at least one of the two higher-order address code codes is zero, the inhibitory potential is applied to the gate input of the decoder 10, and this prevents the selection of the memory block 17. The resolving potential from the output of the element HE 3 is fed to the sample input of the memory block 4 and to the sample input of the register 15, to the second input of which through the element OR 14 the signal from the bits output or input bus 3 of the control is received. In this case, the passage of information from the input of register 15 to its output is permitted. In this way, the two most significant bits go to the address inputs of memory 4 and 17 through the J5 register, via the bus, and access is allowed to program memory 4.

When the cell address is in the second zone of the address field, the two most significant bits of the address code are equal to one and resolvable, and the potential at the output of element I 12 allows the sample signal to pass through the decoder 10 to the input of the sample of the corresponding memory block 17, simultaneously entering the second input of the sampling register 16. In this mode, two registers are written to the outputs of the register (page number). Thus, at the address inputs of memory blocks 4 and 17, an address is formed, the high bits of which are determined by the value recorded in register 16, and the low bits are received directly from the address bus 1.

Register 15 and memory block 4 are disconnected from address bus 1 by supplying a locking signal from the inverter 13 output.

Addressing the field of the program memory block 4 is carried out directly, and the field inside the memory page - indirectly using the lower bits. Higher bits must always be equal to one.

Claims (1)

Invention Formula A RAM addressing device containing two decoders, two AND elements, the first register, whose outputs are connected to the information inputs of the first decoder, whose outputs form a group of device memory block selection outputs, the group of inputs of the second decoder is connected to the device’s bi-directional address bus, the first output of the second decoder is connected to the first inputs of the first and second elements And, the second inputs of which are connected respectively to the input w Output and input of the device, the first element And the connection With the recording entry of the first register, characterized in that, in order to increase the speed of the device when accessing different memory blocks, the second and third registers, the NOT element, the OR element, the third and fourth And elements, the channel transmitter unit are entered into It, informational inputs of which are connected to a group of outputs of the first register, and a group of outputs connected to a bi-directional data bus of the device, the output of the second element I is connected to a control 1m input of the channel transmitter unit, the information inputs of the second register a is connected to the group of high-order bits of the device’s address bus; the second output of the second decoder is connected to the first input of the third element AND, which is connected to the input of the second register; input The output of the device is connected to the second input of the third element AND, and the first input of the OR element, the output of which is connected with the inputs for selecting the second and third registers, the group of high-order bits of the address bus is connected to the inputs of the fourth AND element, the output of which is connected to the enable input of the selection of the second register by a gating input of the second the decoder and the input of the NOT element, the output of which is connected to the input of the selection resolution of the third register and is the output of the selection of the memory block program of the device, input The input of the device is connected to the second input of the IP element bi-directional data bus of the device connected to the information inputs of the first and second registers, outputs The second and third registers of the bit are combined through the mounting OR and form a bi-directional address bus of the higher bits of the device's memory blocks.