SU1410783A1 - Mis integrated circuit structure manufacturing technique - Google Patents

Mis integrated circuit structure manufacturing technique

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Publication number
SU1410783A1
SU1410783A1 SU4017513/25A SU4017513A SU1410783A1 SU 1410783 A1 SU1410783 A1 SU 1410783A1 SU 4017513/25 A SU4017513/25 A SU 4017513/25A SU 4017513 A SU4017513 A SU 4017513A SU 1410783 A1 SU1410783 A1 SU 1410783A1
Authority
SU
USSR - Soviet Union
Prior art keywords
substrate
silicon dioxide
integrated circuit
mis
circuit structure
Prior art date
Application number
SU4017513/25A
Other languages
Russian (ru)
Inventor
В.А. Гогиберидзе
А.И. Красножон
В.С. Паринов
Л.И. Хворов
Original Assignee
В.А. Гогиберидзе
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by В.А. Гогиберидзе filed Critical В.А. Гогиберидзе
Priority to SU4017513/25A priority Critical patent/SU1410783A1/en
Application granted granted Critical
Publication of SU1410783A1 publication Critical patent/SU1410783A1/en

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  • Drying Of Semiconductors (AREA)

Abstract

FIELD: microelectronics. SUBSTANCE: silicon dioxide, photoresist, silicon nitride, and polysilicon layers are formed on working side of substrate; prior to their plasma reactor etching, silicon dioxide layer is formed in uniformly distributed sections, their thickness being at least that equal to layer thickness on working side, on opposite side of substrate. Then MIS transistor regions are formed and contacts for them. More effective gettering of admixtures on substrate underside is ensured which increases reliability of MIS integrated circuits at high temperature. EFFECT: increased output of serviceable structures due to preventing electric breakdown of silicon dioxide layers, up to 75 nm thick, on working surface of substrate during their plasma reactor etching.
SU4017513/25A 1985-10-22 1985-10-22 Mis integrated circuit structure manufacturing technique SU1410783A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU4017513/25A SU1410783A1 (en) 1985-10-22 1985-10-22 Mis integrated circuit structure manufacturing technique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU4017513/25A SU1410783A1 (en) 1985-10-22 1985-10-22 Mis integrated circuit structure manufacturing technique

Publications (1)

Publication Number Publication Date
SU1410783A1 true SU1410783A1 (en) 1994-05-30

Family

ID=60517507

Family Applications (1)

Application Number Title Priority Date Filing Date
SU4017513/25A SU1410783A1 (en) 1985-10-22 1985-10-22 Mis integrated circuit structure manufacturing technique

Country Status (1)

Country Link
SU (1) SU1410783A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2680606C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method of manufacture of semiconductor structures
RU2680607C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method for making semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2680606C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method of manufacture of semiconductor structures
RU2680607C1 (en) * 2018-01-23 2019-02-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Method for making semiconductor device

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