SU1410783A1 - Mis integrated circuit structure manufacturing technique - Google Patents
Mis integrated circuit structure manufacturing techniqueInfo
- Publication number
- SU1410783A1 SU1410783A1 SU4017513/25A SU4017513A SU1410783A1 SU 1410783 A1 SU1410783 A1 SU 1410783A1 SU 4017513/25 A SU4017513/25 A SU 4017513/25A SU 4017513 A SU4017513 A SU 4017513A SU 1410783 A1 SU1410783 A1 SU 1410783A1
- Authority
- SU
- USSR - Soviet Union
- Prior art keywords
- substrate
- silicon dioxide
- integrated circuit
- mis
- circuit structure
- Prior art date
Links
Abstract
FIELD: microelectronics. SUBSTANCE: silicon dioxide, photoresist, silicon nitride, and polysilicon layers are formed on working side of substrate; prior to their plasma reactor etching, silicon dioxide layer is formed in uniformly distributed sections, their thickness being at least that equal to layer thickness on working side, on opposite side of substrate. Then MIS transistor regions are formed and contacts for them. More effective gettering of admixtures on substrate underside is ensured which increases reliability of MIS integrated circuits at high temperature. EFFECT: increased output of serviceable structures due to preventing electric breakdown of silicon dioxide layers, up to 75 nm thick, on working surface of substrate during their plasma reactor etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU4017513/25A SU1410783A1 (en) | 1985-10-22 | 1985-10-22 | Mis integrated circuit structure manufacturing technique |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU4017513/25A SU1410783A1 (en) | 1985-10-22 | 1985-10-22 | Mis integrated circuit structure manufacturing technique |
Publications (1)
Publication Number | Publication Date |
---|---|
SU1410783A1 true SU1410783A1 (en) | 1994-05-30 |
Family
ID=60517507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SU4017513/25A SU1410783A1 (en) | 1985-10-22 | 1985-10-22 | Mis integrated circuit structure manufacturing technique |
Country Status (1)
Country | Link |
---|---|
SU (1) | SU1410783A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2680606C1 (en) * | 2018-01-23 | 2019-02-25 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method of manufacture of semiconductor structures |
RU2680607C1 (en) * | 2018-01-23 | 2019-02-25 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for making semiconductor device |
-
1985
- 1985-10-22 SU SU4017513/25A patent/SU1410783A1/en active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2680606C1 (en) * | 2018-01-23 | 2019-02-25 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method of manufacture of semiconductor structures |
RU2680607C1 (en) * | 2018-01-23 | 2019-02-25 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for making semiconductor device |
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