SU1409949A1 - Frequency instability meter - Google Patents

Abstract

The invention can be used to measure frequency fluctuations of oscillatory sources. The purpose and the invention is to improve the accuracy of measurement of frequency instability. The meter contains line 2 delays, local oscillators 7.1, 7.2, mixers 6.1-6.4, multipliers 8.1 and 8.2 frequencies, amplifiers 9.1 and 9.2 and indicator 18. Amplitude comparators 4.1-4.4, §5 control of analog keys 3.1 and 3.2 are entered into the meter, driver 10 time intervals, reversible counter control unit 11, result registers 13 and 15, result indicators and result indicators 14 and 16, overflow unit 17, control signal generation unit 19, control signals, cycle counter 20 and counting pulse generator 21. Due to this, the effect on the measurement of the intrinsic phase noise of the meter is reduced by using two alternating operating modes: the Measurement mode and the Self-Monitoring mode. 7 il. I rr-nPFFn I ,, g with W cl co with co (co

Description

The invention relates to the field of radio engineering measurements and can be used to measure the frequency fluctuations of stable sources of oscillations.

The purpose of the invention is to improve the accuracy of measurement of frequency instability by reducing the effect on the measurement result of the intrinsic phase noise of the meter by using two alternating operating modes: the Measurement mode and the CaMOKoHTpojrib mode,

Fig. 1 shows a diagram of the generators of frequency instability in generators; Fig. 2 shows timing diagrams explaining the operation of the control unit of analog keys; Fig. 3 shows timing diagrams explaining the operation of the time interval generator; Fig. 4 is a diagram of the control unit for the inputs of the reversible counter; Fig. 3 shows timing diagrams explaining the operation of the control unit for the inputs of the reversible counter; Fig. 6 is a block diagram of the control signal generation unit; Fig. 7 shows timing charts explaining the operation of the control signal generation unit.

The frequency instability meter contains (Fig. 1) a two-channel frequency comparator 1, a delay line 2, the input of which is connected to the device input and the first input of the two-channel frequency comparator 1, two analog switches 3.1 and 3.2, connected by their outputs to the second input two-channel frequency comparator 1, the input of the first analog switch 3.1 is connected to the output of the delay line 2, and the input of the second analog switch 3.2 is connected to the input of the device, four amplitude comparators 4.1-4.4, the input of the first amplitude comparator 4.1 n is connected to the input of the device, and the input of the second amplitude comparator 4.2 is connected to the output of the delay line 2, the analog key control unit 5, the first input of which is connected to the output of the first amplitude comparator, and the second input of the analog key control unit 5 is connected to the output of the second amplitude comparator, The first and second outputs of the control unit 5 with analog switches are connected to the control inputs of the first 3.1 and the second 3.2 analogue, respectively.

g

. d

5 0 5 "

0 5

five

0

five

the keys, the mixer mixer 6 ,, 1-6.4, the first input of the first loader 6,1 is the first input of the two-channel frequency comparator 1, and the first input of the third mixer 6.3 is the second input of the two-channel frequency comparator 1, two local oscillator 7,1 and 7; 2, the output of the first local oscillator 7.1 is connected to the second inputs of the first 6.1 and third 6.3 mixers, and the output of the second local oscillator 7.2 is connected to the second inputs of the second 6.2 and fourth 6.4 mixers, two multipliers 8.1 and 8.2 frequencies connected by their inputs to the outputs of the first 6.1 and third respectively 6.3 mixers, and the outputs of the multipliers 8.1 and 8.2 frequencies are connected to the first inputs of the second 6.2 and fourth 6.4 mixers, two amplifiers 9.1 and 9.2, whose inputs are connected to the outputs of the second 6.2 and fourth 6.4 mixers, and the outputs of amplifiers 9.1 and 9.2 are, respectively, the first and second outputs of frequency comparator 1, shaper 10 time intervals, the first and second inputs of which are connected respectively via the third 4.3 and fourth 4.4 amplitude comparators with the first and second outputs of the two-channel frequency h omparatora 1, unit 11 pack reversible counter inputs connected by their first and second inputs respectively to the first and second outputs of the generator 10 time intervals, reversible binary-decimal counter 12, summing and subtracting whose inputs are connected respectively to the first and second outputs of the reversible counter input control unit 11 , the result register 13, the input information bus of which is connected to the corresponding output information bus of the reversible counter 12, the result indicator 14, the input bus of the cat The op is connected to the output bus of the result register 13, the result sign register 15, whose information input is connected to the third output of the reversible counter input control unit 11, the result sign indicator 16, the input of which is connected to the output of the result sign register 15, the overflow block 17 connected by its first input with output of overflow counter

12, an overflow indicator 18 connected by an input to an output of an overflow unit 17, a control signal generating unit 19, the first input of which is connected to a third output of the time generator 10 time slots, a cycle counter 20, the input of which is connected to the first output of a 19-channel frequency output unit the comparator 1 and the input of the first amplitude comparator 4.1, and the second input of the two-channel frequency comparator 1 receives a signal in the form Ud, 5 (t) A (t.- t) cos wo (t - t) + q (t - -t, ) (t signal delay time line 2 delay) through the first ana

the control signal and the key lag 3.1 or the unattended input of the control unit 5 is a signal via the second analog key 3.2 depending on the phase of the control signals at the first and second outputs of the analog control unit 5. The amplitude comparator 4.1 generates a sequence of square-wave pulses, corresponding to the level of p 1, and the time of existence of the pulse corresponds to the duration of the positive half-cycle of the signal. The output signal of the first amplitude comparator 4.1 takes the form shown in Fig. 2a.

using the keys, a pulse generator 21, the output of which is connected to the second input of the control signal generation unit 19 and the third input of the control input input unit 11 of the reversible counter, the fourth input of which is connected to the output of the reversible counter loan 12, while the second output the control signal generation unit 19 is connected to the control inputs of the result sign register 15 and the result register 13, the third output of the control signal generation unit 19 is connected 25 to the second input of the overflow unit 17 and the th input of the control input 11 of the reversible counter, the sixth input of which is connected to the fourth

the output of the control-shaping unit 19 forms a pulse from the signal

40

The fifth input of the analog key control unit 5 is connected to the sixth output of the control signal generation unit 19, the third input of which is connected to the counter output of 20 cycles.

The control unit 11 (FIG. 4) forms an OR element 22, the inverse output of which is connected to the counting input of the trigger 23, the outputs of which are connected to the inputs of the AND-NE elements 24-27, the outputs of which are connected through the AND-NOT elements 28 and 29 with inverter outputs 30 and 31.

The control signal generation unit 19 (Fig. 6) contains (Fig. 6) a trigger 32, the output of which through an AND-NE element 33 is connected to a counter 34 of the counter 34, a decoder 35, an OR-NOT element 36, a trigger 37, 38-41 inverters and trigger 42.

The device. Works in the following way.

The analog input signal is Ugy (t) A (t)) t + l / (t). This signal is sent to the first input.

45

55

the sequence shown in fige. This signal is fed to the second input of the analog key control unit 5. The control unit 5 forms with analog keys under the action of control signals (Fig.26, c), coming to its third and fourth inputs (level 1 on the fourth input corresponds to the Measurement mode, and level 1 on the third input - to Self-checking mode) the signals at their first and second outputs, which control the operation of analog switches 3.1 and 3.2. In the Measurement mode of operation, the first input of the two-channel frequency comparator, 1, sends an input test signal, and a second signal delayed at its second input. In the Self-monitoring mode, the second input is given an input signal that is not set. In addition, to ensure minimal transient processes in the two-channel frequency co-parator 1, it is necessary to ensure the supply of analog signals to the second input of the two-channel frequency comparator 1 only at the moments of transition of this signal through the O or 180 phase

den key 3.1 or undelayed

signal through the second analog key 3.2, depending on the phase of the control signals on the first and second outputs of the analog key control unit 5. The amplitude comparator 4.1 generates a sequence of square-wave pulses, corresponding to the level of p 1, and the time of existence of the pulse corresponds to the duration of the positive half-cycle of the signal. The output signal of the first amplitude comparator 4.1 takes the form shown in Fig. 2a.

This signal is fed to the first input of the analog key control unit 5. The output signal of the line-delay is fed to the input of the second amplitude comparator 4.2, which is 40

0

five

five

the sequence shown in fige. This signal is fed to the second input of the analog key control unit 5. The analog key control unit 5 generates under the action of control signals (Fig.26, c), sent to its third and fourth inputs (level 1 on the fourth input corresponds to the Measurement mode, and level 1 on the third input - to the Self-monitoring mode) the first and second outputs that control the operation of the analog keys 3.1 and 3.2. In the Measurement mode of operation, a test signal is input to the first input of a two-channel frequency comparator, 1, and a signal delayed by a delay line 2 is fed to its second input. In the Self-control mode, an input non-delayed signal is applied to the second input. In addition, to ensure minimal transients in the two-channel frequency comparator 1, it is necessary to ensure the supply of analog signals to the second input of the two-channel frequency comparator 1 only at the moments of transition of this signal through the O or 180 phase,

This function is performed by an analog key control unit 5,

In accordance with the logic of operation of the moment t to t on the first output (fig.2d) of block 5 there is a pulse corresponding to level 1, and on the second output from tj to tj - level O. From the moment t and on the first output there is a level O , and on the second exit from the moment 1. From

tg - level

this follows.

that the analog key 3.1 from t to t j is open, and the key 3.2 is closed — this corresponds to the operation of the device in the mode: the measurement. From t to tj, both keys 3.1 and 3.2 are locked. From the moment tj the analog key 3.2 is opened, and from the moment tj onwards the key 3 .1 is closed, this corresponds to the role mode.

 The self-signals on the outputs of the two-channel frequency comparator 1 also contain the self-noise of the two-channel frequency comparator.

The output signals of the two-channel frequency comparator 1 (Fig. 3a) proceed further to the third and fourth amplitude comparators, from which the pulse sequences shown in Fig. 36c are formed.

Pulse sequences thus formed are distinguished by their duration due to the instability of the frequency of the signal under investigation and the instants of appearance due to the presence of a delay line 2 and the instability of the frequency of the signal.

Calculating the difference in durations of output pulses in series - flocks you can get the desired information about the frequency instability of the signal under study in the form of Uy (t)

ifitLi-iflt-iEiL

 Sign

m Wpt-j, +

mt.

 h

+ (t) J | sign mwe t + mt j-i3U) (t) +. + cr (t), where yi) t

 . f.lEiti).

there is nothing more than an unstable frequency of the signal under study at a sufficiently small value; p (t) is the difference in the intrinsic noise of the measuring channels of the two-channel clock. total comparator 1.

The process of determining the difference of durations and myelastic ones is carried out in two stages. At the first stage, the shaper 10 of time intervals generates a preliminary difference, and at the second stage the reversible counter 12 calculates the final difference, which is registered by the result register 13 and indicated by the indicator 14.

The time interval is excluded from the signals (fig. 3b, c) when both of them are simultaneously present on the first and second inputs of the former 10. The final difference between the durations of the pulse sequences is calculated by calculating the modulus of the difference and the sign of the difference of the formed pulse sequences (FIG. 3d, d ) a reversible counter 12. The block 11 controls the operation of the reversible counter 12 so that the first incoming pulse (Fig. 3d or e) is fed to the summing input of the reversible counter

12, and a second pulse is applied to the subtract input. As a result of this, the difference A is formed, and the sign of times

five

0

from the first pair of pulses, i

Let us consider in more detail the operation of the control block 11 (Fig. 5). Let for a certain time interval, the first and second inputs of block 11 are received in one pulse, the occurrence of which preceded the installation in O of all bits of the reversible counter 12, the initial installation of trigger 23 (FIG. 4) of block 11, i.e. The device is in Measurement mode. A first pulse, for example, which arrived at the second input (FIG. 4) permits the arrival of pulses with a reference repetition frequency from the generator 21 of counting pulses to the subtraction output of the reversing counter 12 (Fig. 3a). Under

5 the action of the front of the first pulse counter 1 2 generates a signal 0 (loan), which is fed to the fourth input of the block 11. This impulse triggers trigger 23 (fig.Zg), after h.

0 counting pulses (fig.Zd) are fed to the summing input of the reversible counter 12. After that, a pulse arrives at the first input of block 11 (fig.Zb) and block 11 allows the counting pulses to pass to the subtracting input of the reversing counter 12. The contents of the counter 12 are reduces If the pulse duration on fig.Zb longer duration

a pulse in FIG. 3b, then at the moment when the contents of counter 12 becomes zero, a signal appears at the output of counter 12 and at the fourth input of block 11, which overturns trigger 23 (figure 4) of block 11 and permits the passage of counting pulses to the input of the summation of the counter 12 subsequent pulses (fig.Zd). Thus, in the counter 12, a number equal to the difference d of the durations of the first pair of pulses (Fig. 56, c) is formed, and the level O on the third output of the block 11 corresponds to the positive sign of the difference L,. The subsequent pairs of pulses are processed similarly to the first pair, only the initial state of the counter 12 is equal to the value of the previous difference L obtained.

1.2 ...

At the third output of the former 10, level 1 appears only when there is no signal on its first or second input (Fig. 5l). The pulse thus formed (Fig. Ze) from the third output of the driver 10 is fed to the net input of the control signal generating unit 19. A positive signal edge (Fig. 76) sets the output Q of the flip-flop 32 (see Fig. 6) to level 1 (Fig. 7b), allowing the passage of pulses of the clock frequency (Fig. 7a) from the second input of block 19 (Fig. 6) through the element AND-NO 33 on the input of the binary-decimal counter 34 (Fig.7). The bits of the counter 34 are connected to the corresponding inputs of the decoder 35 of the binary-decimal code to the positional one. The decoder 35 generates at its outputs time-shifted pulses (fig.7d, g). By the eighth pulse (fig. 7z), the trigger 42 is transferred to the opposite state. The output signals of the flip-flop 42, which are out of phase relative to each other (fig.7p, p), are received respectively at the third and fourth inputs of the analog key control unit 5 and, under their action, the device switches from the Measurement mode to the Self-Monitoring mode. The formation of the value in the counter 12 is similar to the process considered. At the same time, the output signal at the fourth output of the block 19 is fed to the sixth input of the control block 11 in the form shown in FIG. 7e, changes the trigger state

five

0

five

0

five

23 (FIG. 4) to the opposite, ensuring that the difference is obtained - id, -c / in the counter 12. After the end of the Self-Monitoring mode, the device switches to the Measurement mode, etc. IB, as a result of alternating a certain number of measurement cycles and the control itself, in counter 12, an average value of f 4 (t) - - (t) is formed, which is entered into a register

13 results and is indicated by the indicator 14. The sign of the result is entered

The register is 15 characters and is indicated by an indicator 16 characters. If at the calculation of the value of Cu (t) - (t) at least once the counter 12 overflows, the overflow block 17 sends a signal to indicator 18 equal to 1. Such a result of the calculation does not carry reliable information about the measured value, and its should be excluded from consideration, and the counter size 12 should be increased. If the current measurement cycle or self-control is constant in a series of cycles (the number of cycles is determined by the division factor of the counter 20 cycles), then the transition in this cycle from the Measurement mode to the Self-Control mode under the action of the signal (fig.7p) at the first output of the block 19 generating control signals, a binary-decimal counter 20 of the number of measurement cycles and self-control form at its output and at the third input of block 19 a signal O. This signal switches the trigger 37 (Fig. 6) to the opposite state, and at the output of inverters 38 and 39 pos the level O, the resolution of the formation of the signal at the second and then at the third and fifth outputs of block 19. These signals are allowing to write to the register 13, and then zeroing the reversing counter 12, the initial setting of the trigger 23 of block 11, trigger 42 of block 19, and reset of overflow block 17. The last control signal (fig.7z) from the eighth output

0, the decoder 35 (Fig. 6) resets the trigger 32, sets the level O at the outputs of the counter 34, changes the state of the trigger 42 of the operating modes to the opposite. Indicators

14. and 16, indicate the measurement result in the form of a decimal number and a sign of the result until the time of overwriting in registers 13 and 15 of the next result. Subtract from current pe5

ultat L in the Measurement of the current result mode (I || in the Self control mode and the formation of the averaged difference in the form of l (t) - c / (t) equal to the value of the instability of the frequency of the signal under study, allows the order and more to reduce the effect the inherent phase noise of (t) of the measuring channels of the two-channel frequency comparator 1. At the same time, the measurement accuracy is improved. The use of two modes of Measurement and Self-control is effective only for those phase and amplitude noises that have a correlation interval much longer than the time and to carry out measurements and self-control,

Claims (1)

Invention Formula A frequency meter that contains a delay line, two local oscillators connected in series to the first mixer, a first frequency multiplier, a second mixer and a first amplifier, a third mixer connected in series, a second intelligent frequency amplifier, a fourth mixer and a second amplifier, the output of the first local oscillator is connected to the second inputs the first and third mixers, and the output of the second local oscillator with the second inputs of the second and fourth mixers, the first input of the first mixer is the input of the meter and the connection with the input of the delay line, and the outputs of the first and second amplifiers are connected to an indicator, characterized in that, in order to improve the measurement accuracy, two analog switches, four amplitude comparators, a time interval generator, a reversible counter, a control unit for the reversible counter inputs are introduced into it , control signal generator unit, cycle counter, analog key control unit, result register, result sign register, overflow unit, counting pulse generator, result sign indicator and overflow counter overflow indicator 45 of the result sign register and result register, whose input bus is connected to the output bus of the reversible counter, and its output bus to the input bus of the result indicator, the output of the reversible counter loan is connected to the fourth input of the reversible counter input control unit, the fifth the input of which is connected to the third output of the unit The output of the delay line is connected to the input of the second amplitude comparato-55 generating control signals, pa and through the first analog switch the fourth output of which is connected to the input of the second mixer and the output by the sixth input of the control unit of the input of the analog switch, the first counter of the reversible counter, The analog input of the analog key controller whose output is connected to the input ten 15 20 , jg and 409949.10 connected to the output of the second analog switch, the second input of the analog switch control unit is connected to the output of the first amplitude comparator, the input of which is connected to the inputs of the delay line and the second analog switch, the first and second outputs of the analog switch control unit are connected to the control inputs of the first and second analog switches, the first and second inputs of the time interval generator are connected respectively to the outputs of the third and fourth amplitude comparators, whose inputs are the first and second outputs of the time interval generator are connected respectively to the first and second inputs of the control unit for the inputs of the reversible counter, and its third output is connected to the first input of the control signal generation unit, the first and second outputs of the input control unit. the reversible counter is connected respectively to the summing input and the subtracting input of the reversible counter, and the third output of the reversible counter input control unit is connected to the information input of the reversing counter istra sign of the result, an output connected to an outcome indicator mark count pulse generator output is connected to the third input 35 of the input counter control unit and the second input of the control signal generation unit, the third input of which is connected to the output of the cycle number counter, the input of which is connected to the third input of the analog key control unit and the first output of the control signal generating unit, the second output of which connected to the control inputs 45 of the result sign register and the result register whose input bus is connected to the output bus of the reversible counter, and its output bus to the input bus of the indicator p result, yield loan down counter is connected to a fourth input of the control unit inputs down counter, a fifth input connected to the third output of block thirty 50 o-55 generation of control signals, the fourth output of which is connected to the sixth input of the control unit for the inputs of the reversible counter, the fifth output of which is connected to the input / U7 / 7 tf iz t j Fia2 Outlet Out Ppppp ppppppppp b 6 shh Well c Fy pppp about one- FIG. five Viadz and vlod 1 Pppppppppppp one ppppp I P P bycoE (01. St / jHiff} SttxoSS Ppppp one P i t – t t t t Jb Jt t t t t t t