SU1405028A1 - Program control module - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in the trunk-modular systems of programmed control of the electric drive. The aim of the invention is to enhance the functionality by programming the minimum movement speed. The software-controlled module includes a pulse generator 1, the first and second controlled dividers 2 and 3 frequencies, the 4th target register, the reversing counter 5, the summing up acceleration counter 6, the subtracting displacement counter 7, the coincidence unit 8, the first driver 9, the multiplexer 10, the first and second elements AND 11 and 12, the RS trigger 13, the element OR 14, the subtracting counter 15, the maximum speed, the second driver 17, the first and second D-triggers 18 and 19, the third element AND 20. The advantage of the invention is in extending the functionality and increasing productivity machines actuated by optimizing the dynamic performance. 5 cl

Description

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The invention relates to automation and computer technology and can be used in trunk-modular software systems for controlling electric drives, such as plotters, coordinate tables, program-controlled automata, or industrial robots.

The purpose of the invention is to expand the function-jQ which is transformed first by the control capabilities by programming the minimum speed of movement.

FIG. Figure 1 shows the structurally variable frequency divider 2 at the output frequency, and its second output is the output of the acceleration-deceleration frequency, which is converted by the second control

the splitter frequency 2 is output to the output frequency, and its second output is the output of the acceleration-deceleration frequency, which is converted by the second control

functional diagram of the module; 2–55 emitted divider 3 frequencies into frequency

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job register structure; figure 3 is a structural diagram of the multiplexer; Fig. 4 is a schedule for testing a given movement; in fig. 5-possible directions of movement depending on the values controlled by the input of the multiplexer.

The module (Fig. 1) contains generator-ator i, first and second controlled dividers 2 and 3 frequencies, register 4 tasks, reversing pulse counter 5, summing counter 6 acceleration, subtracting displacement counter 7, block 8 matches, first shaper 9 multiplexer 10, the first and second elements And 11 and 12, RS-trigger 13, element OR 14, subtracting the counter 15 maximum speed, the register 16 minimum speed, the second driver 17, the first and second D-triggers 18 and 19, as well as the third element and 20.

As controlled dividers 2 and 3 frequencies, for example, a chip 155IE8 bKO.348: 006 TUP, for which the division factor depends on the code on the control inputs, can be used.

In the Acceleration-2 module, a microcircuit can also be applied, for example, a Programmable Timer KP 580 VI53, and on one such microcircuit a subtracting counter 15, maximum speed, subtractive displacement counter 7 and the first driver 9 can be simultaneously implemented. Acceleration-2, since the specified microcircuit allows you to store the original codes. Consequently, there is no need for setting the maximum speed and the amount of movement at the beginning of each movement cycle, by 40 degrees.

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counting the counter counter 5 impulses, which characterizes the magnitude of the acceleration-deceleration. Regis 4 assignments accept data from the trunk and stores the acceleration-deceleration magnitude code that determines the division ratio of the second control divider 3 frequencies, as well as the values of the control signals x, -x, y, for multiplexer 10 and the sign a bot that determines the state of the bus. Acceleration resolution. A reversible counter of 5 pulses summarizes the pulses of the acceleration-deceleration frequency during acceleration and subtracts during deceleration, its bit outputs determine the division ratio of the first controlled divider 2 frequencies.

The summing counter 6 accelerates the counting of acceleration pulses, and the read movement counter 7 subtracts each output frequency pulse from the value of the specified displacement, and its zero output indicates the end of the working of the specified displacement. The coincidence unit 8 determines the start time of the deceleration by comparing the current code of the subtracting displacement counter 7 with the number of acceleration pulses of the acceleration totalizer 6, and the first shaping unit 9 generates an output pulse with the specified parameters, for example, duration.

The multiplexer 10, depending on the values of the control inputs, pulses the output frequency to one and the outputs X, -X, y, -y, or one of the output pairs (+ x. + Y), (x, -y), (-x , -y), (-X, y). The first and second elements And 11 and 12 allow the counting of the reverse counter of 5 pulses, respectively, during acceleration or deceleration. RS trigger 13 controls resolution

For example, the values of the maximum and minimum travel speeds can be set once at the beginning of work, which improves the performance of the Acceleration-2 module.

Oscillator 1 produces a constant frequency, with its first output being the reference frequency output.

The splitter frequency 2 is output to the output frequency, and its second output is the output of the acceleration-deceleration frequency, which is converted by the second controlled splitter 3 to the frequency

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counting the counter counter 5 pulses, which characterizes the magnitude of the acceleration-deceleration. Register 4 accepts tasks from the data highway and stores the acceleration-deceleration magnitude code that determines the division ratio of the second controllable divider 3 frequencies, as well as the values of the control signals x, -x, y, -y for multiplexer 10 and the indication of operation, bus status Enable acceleration. The reversible pulse counter 5 adds up the acceleration-deceleration frequency pulses during acceleration and subtracts during deceleration, its discharge outputs determine the division ratio of the first controlled divider 2 frequencies.

The totalizing acceleration counter 6 counts the acceleration pulses, and the subtractive displacement counter 7 subtracts each output frequency pulse from the value of the specified displacement, and its zero output indicates the end of the testing of the specified displacement. The coincidence unit 8 determines the start time of deceleration by comparing the current code of the subtractive movement counter 7 with the number of acceleration pulses of the acceleration summing counter 6, and the first driver 9 generates output pulses with predetermined parameters, such as duration.

The multiplexer 10, depending on the values of the control inputs, pulses the output frequency to one of the outputs X, -X, y, -y, or to one of the output pairs (+ x. + Y), (x, -y), (-x , -y), (-X, y). The first and second elements And 11 and 12 allow the counting of the reversible counter 5 pulses, respectively, overclocking or braking, respectively. RS trigger 13 controls resolution

braking, and the element OR 14 resets the first D-flip-flop 18, which controls the resolution of the acceleration, thereby prohibiting acceleration. The subtracting counter 15 of the maximum speed subtracts each pulse of the acceleration-deceleration frequency from the code corresponding to the maximum speed, and its zero output indicates that the maximum speed has been reached.

Register 16 of the minimum speed Stores the code value corresponding to the minimum speed of movement, and also transmits this value to a reversible counter 5 pulses. The second D flip-flop 19 controls the motion resolution, i.e. allowing the passage through the third element AND 20 of them g pulses of the reference frequency to the clock input of the first controlled splitter 2 frequency when issuing the sign of working out a given movement by the second driver 17.

The module works as follows.

Before starting, the module (Fig. 1) is reset.

the input of the reversible counter 5, the summing input of the reversible counter 5 and the input of the first controlled divi- sion. tel 2 frequencies.

To the clock inputs of the first and second controlled dividers 2 and 3 frequencies, respectively, the reference frequency F is fed through the third element AND 19

10 (maximum permissible frequency at the output of the module) and frequency of acceleration and deceleration F, (maximum permissible frequency of acceleration of the module).

Output frequencies G ,, and F, are

15 are independent, because they provide independent parameters: F is the speed of movement of the electric drive, F, is the acceleration value during acceleration and deceleration. In this case, the frequency F is selected

20 at the maximum permissible speed of movement of the electric drive and equal to the maximum permissible frequency at the coordinate outputs of the module, and F, at the maximum permissible value

25 acceleration acceleration braking.

The frequency of the pulses at the outputs of the controlled frequency dividers is determined by the division factor — the code arriving at their control inputs.

(for example, with the Z and C commands when done, the pulse frequency F at the output of the second modulation in the CAMAC standard).

At the beginning of the cycle, the register 4 tasks (Fig. 2) is filled in from the data highway, where the acceleration-deceleration acceleration value code is entered, the value of the control of the input of the multiplexer 10 (Fig. 3), depending on the required direction of movement and the characteristic Work, The starting module, as well as the code of the magnitude of the required movement in the subtractive movement counter 7, the code of the maximum movement speed in the subtracting counter 15 of the maximum speed and the code of the maximum movement speed in the register 16 of the minimum speed.

The information in the register 4 of the task must be entered after the information is entered into the counters 7 and 15. and the register 16, since with the occurrence of 1 in the category of operation the module starts.

at the initial moment, before setting to 1. sign Work in the register 4 tasks, outputs of the triggers 13) 18 and 19 are set to O and, thus, prohibit the transmission of impulses, respectively, to triggering

go controlled divider 3 frequencies n - F,

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35 where n is the code corresponding to the specified acceleration-deceleration acceleration, coming from the register 4 tasks to the control inputs of the divider 3 frequencies.

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Pulses with a constant frequency F, corresponding to a given acceleration, arrive at the first inputs of elements II and 12. When the symptom is established, the register of task 4 in 1 the second driver 17 generates a short pulse that overwrites the value of the minimum speed of movement from the register 16 of the minimum speed to reversing counter 5. On the trailing edge of this pulse, the triggers 18 and 19 are set to 1. These triggers open the first element 11 and the third element 20, respectively. The frequency corresponding to the code of the value acceleration braking speed, i.e. the division ratio of the second controlled splitter 3 frequencies, is applied to the summing

the input of the reversible counter 5, the summing input of the reversible counter 5 and the frequency 2 at the input of the first controlled divider.

To the clock inputs of the first and second controlled dividers 2 and 3 frequencies, respectively, the reference frequency F is fed through the third element AND 19

(the maximum permissible frequency at the output of the module) and the frequency of acceleration and deceleration F, (the maximum permissible frequency of acceleration of the module).

Output frequencies G ,, and F, are

independent, because they provide independent parameters: F is the speed of movement of the drive, F, is the acceleration value during acceleration and deceleration. In this case, the frequency F is selected

at the maximum allowable speed of movement of the drive and equal to the maximum allowable frequency at the coordinate outputs of the module, and F, at the maximum allowable value

accelerate acceleration braking.

The frequency of the pulses at the outputs of the controlled frequency dividers is determined by the division factor — the code received at their control inputs.

the frequency of the pulses F at the output of the second controlled divider 3 frequency n - F,

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35 where n is the code corresponding to the specified acceleration-deceleration acceleration, coming from the register 4 tasks to the control inputs of the divider 3 frequencies.

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Pulses with a constant frequency F, corresponding to a given acceleration, arrive at the first inputs of elements II and 12. When the symptom is established, the register of task 4 in 1 the second driver 17 generates a short pulse that overwrites the value of the minimum speed of movement from the register 16 of the minimum speed to reversing counter 5. On the trailing edge of this pulse, the triggers 18 and 19 are set to 1. These triggers open the first element 11 and the third element 20, respectively. The frequency corresponding to the code of the value acceleration braking speed, i.e. the division ratio of the second controlled splitter 3 frequencies, is applied to the summing

5 counts reversible counter input. The pulses to the summing input of the reversible counter 5 are received until long until the reset signal of the acceleration resolution is received from the element OR 14, i.e. reset the trigger 18. The trigger 18 also allows the counting summing counter 6 acceleration and subtracting counter 15 maximum: speed. Thus, the totalizer of the acceleration counter 6 stores an information about the number of pulses j that the module outputted during the aezgon time.

Simultaneously with the filling of the rever- sion (counter 5, the subtractor; the maximum speed is calculated; and

acceleration, the element I 11 is closed and the filling of the reversible counter 5 pulses is stopped. Further, if the acceleration prohibition was caused by the achievement of the maximum speed, as evidenced by the pulse at the zero output of the subtracting counter 15, the maximum speed containing at this moment

code O, the movement is carried out at a constant speed .c before the occurrence of the signal at output 8 of the match. The maximum speed of the movement corresponds to the maximum code value of the reversible counter of 5 pulses. Moreover, during acceleration to the maximum speed, the code at the output of counter 5 varies from N to N linearly. If a

Filling of the acceleration is also caused by the summing up of the counter for acceleration and subtraction: of the 7 displacement of the output controlled frequency Fgjjij of the first controlled divider 2 frequencies, on the control inputs of which the current code of the Islamic N reversing counter of 5 pulses is fed . Consequently, the frequency varies in proportion to the number N:

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1 | 1In this, the acceleration and torpedo- • tion paths are as close as possible to the natural acceleration and deceleration trajectories of the electric drives, thereby ensuring optimal control of the FL.

I Pulses of the output frequency Rc, are formed by the first shaper of 9 MPs, from the output of which with a given duration, for example 0.5 μs, are fed to the input of the multiplexer 10 (Fig. 3). The generated frequency pulses are switched in the Multiplexer 10 in accordance with the beginnings of the control inputs defined by the register 4 tasks (Fig. 2) T (here the displacement is specified in one of eight possible directions (Fig. 5).

When the maximum speed is reached (displacement 1 is specified (| FIG. 4) or when comparing the codes of the scores 6 and 7, displacement 1, that C sees to work on accelerating half of the specified transmittance, and the second half should be 6feiTb worked through braking, collecting - Removed s trigger trigger 18

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of a given displacement on acceleration, the signal is greater than or equal to the output of block 8, the coincidence prohibits acceleration by resetting the trigger 18 5 of the resolution of acceleration through the OR element 14 and sets the trigger 13 of the deceleration resolution to the unit state which allows subtraction of the reversible counter of 5 pulses and the displacement occurs with braking. In this case, pulses with a frequency F through the element I 12 are fed to the subtracting input of the reversible counter of 5 pulses, the code of which N decreases linearly, decreasing in proportion to the frequency P ,,. If the number of pulses of a given movement in the movement counter 7 (for a given movement L1, FIG. 4) is even, then the coincidence unit 8 generates a signal when the acceleration counter 6 and the movement counter 7 are equal, if the number of pulses is odd, the coincidence unit 8 outputs a signal when the code in the counter 6 acceleration is 1 more than the code in the counter 7 movement.

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When processing a given movement with the maximum speed reached, the block 8 coincides with a signal indicating that the remaining pulses of the specified movement (stored in the counter 7) must be processed with deceleration. At the same time, an equal number of pulses during acceleration and deceleration is tested, since counter 6 records the number of impulses processed in the acceleration mode (until the maximum speed is reached).

The braking stops when the module completes a specified movement, as evidenced by the impulse at the zero output of the subtractive displacement counter 7, which currently contains O code. This impulse also resets the totalizing acceleration counter 6, the braking placement trigger 13 to O , prohibits braking and -blocking through the element AND 20 flow

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pulses of frequency F for the first control of the module by approximately 25% due to the possibility of programming the value of the maximum speed of movement; an increase in the productivity of controlled automata by about 20% due to the possibility of optimizing the dynamic characteristics, including the magnitude of the minimum speed of movement.

These advantages provide an increase in the efficiency of the mainstream modular software systems of electric drive control, for example, in graph plotters, coordinate tables, software-controlled machines or industrial robots, as well as the functioning of software with computer control and computing equipment in general.

It is a divider of 2 frequencies, thus the frequencies at the outputs of the module. This pulse is a request signal confirming that the module is ready to complete the next cycle and enters the data line. Thus ends the cycle of testing by the module of a given displacement.

As a result, the module is in the following state: the summing up counter b of overclocking and the subtracting counter 15 of the maximum speed are reset to O, the triggers 13, 18 and 19 permitting the operating modes of the module are O. The state of the reversible counter 5 is indifferent, since at the beginning Each cycle overwrites the contents of the minimum speed register 16 into this counter.

Thus, the module prepares to receive a new motion task. By assigning various speed codes to the minimum speed register 16, it is possible to change the speed at which the engine begins to work out a specified displacement amount, i.e. It is possible to optimize the dynamic characteristics of controlled electromechanical drives.

From the description of the work of the module, it follows that, compared with the known module, the proposed implementation implements a fundamentally new way of organizing the movement of the electric drive with acceleration and deceleration, in which, along with the possibility of programmatically controlling the values of acceleration and deceleration, maximum and minimum movement speeds, the moment of the start of deceleration is automatically determined on the basis of the control of the unitary code, which is formed with the output frequency of the module, with the last pulse given 30

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Claims (1)

Invention Formula A software-controlled module containing a pulse generator, the first and second elements And, RS-trigger, ma-. data hub, an OR element, the first controlled frequency divider, the control inputs of which are connected to the bit outputs of the reversible pulse counter, the second control frequency splitter, the control inputs of which are connected to the first control outputs of the register of the reference, the second control signals which are connected to the control inputs of the multiplexer, the clock input of which is connected to the output of the first pulse shaper, the first and second information inputs of the match block are connected respectively to the information ion outputs of a summing counter, acceleration pulses, and a subtracting pulse counter for movement, the zero output of the subtractive motion pulse counter is connected 1405028 movement is also the last braking impulse The well-known software-controlled module is characterized by the impossibility of programming the minimum movement speed, which explains its functional limitations. According to the above analysis and calculation, approximate data on the achieved effect were obtained when using a software-controlled module -: functional expansion Invention Formula A software-controlled module containing a pulse generator, the first and second elements And, RS-trigger, ma-. data hub, an OR element, the first controlled frequency divider, the control inputs of which are connected to the bit outputs of the reversible pulse counter, the second control frequency splitter, the control inputs of which are connected to the first reference register control outputs, the second control signals which are connected to the control inputs of the multiplexer, the clock input of which is connected to the output of the first pulse shaper, the first and second information inputs of the match block are connected respectively to the information ion outputs of a summing counter, acceleration pulses, and a subtracting pulse counter for movement, the zero output of the subtractive motion pulse counter is connected with bus End of operation, data line is connected to information inputs of the register of the task, information inputs of the subtracting pulse counter of maximum speed and with bus End of work, the second output of the pulse generator is connected to the counting input of the second controlled frequency divider, the output of which is connected to the first input of the first And element and the first input of the second element I, the second input of which is connected to the direct output of the RS flip-flop, the R input of which is connected to the bus End of work, and the S input to the first input of the element OR and you by the coincidence block, the second input of the OR element is connected to the output of the subtracting pulse counter of maximum speed, the summing and subtracting inputs of the reversible counter of pulses are connected to the outputs of the first and second elements, respectively, that, in order to extend the functionality by programming the minimum movement speed, a minimum speed register, a second pulse shaper, the first and second D-flip-flops, a third AND element, whose output is connected to the input of the first controlled frequency divider, the first and second inputs of the third element And are connected respectively to From the highway.  L  H h h   ,P  modle bleu Great cskor 2 five the first output of the pulse generator and with the direct output of the first D-trigger, the C input of which is connected to the C input of the second D trigger, with the control input of the reversible pulse counter and the output of the second pulse driver, the input of which is connected to the third output of the job register, the R input of the first D-flip-flop is connected to the bus. End of operation, the R-input of the second D-flip-flop - with the output of the OR element, the information inputs of the first and second D-flip-flops are permanently connected to the bus of the logical unit, direct output The second D-flip-flop is connected to the input ohm resolution resolution of the subtracting pulse counter of the maximum speed, with the second input of the first element I and with the input resolution of the counting counter of the acceleration pulse counter, the counting input of which is connected to the counting input of the subtracting pulse pulse counter and with 5 by the output of the first pulse generator, the reset input of the summing pulse counter for acceleration is connected to the bus. the outputs of the software-controlled module. 0 II P h .f  pack C F Max ./2 max in F / / I . i I -TO I J  Ij one I l  Thor j Atj Fi &. ) {, if -e -X, -if . Have l .x Fa g 5