SU1402268A3 - Device for timed switching - Google Patents

Description

(21) 2575197 / 24-09

(22) 02.02.78

(31) 766369

(32) 07.02.77

(33) US

(46) 07.06.88. Bul Number 21

(71) International Standard Electric Corporation

(72) Kenneth Frank Gisken (US) and John Michael Cotton (CI)

(53) 621.395.658 (088.8)

(56) Prager E., Trika J. Electronic telephone stations. M .: Svy, in 1976, p.118.

(54) DEVICE FOR TEMPORARY SWITCHING

(57) The invention relates to telephone communication systems with temporary sealing. The purpose of the invention is to increase the number of switched paths. The device contains a synchronization unit 1, a storage unit 2, n decoders ,, A serial-parallel register 4, n blocks 5, -5 „delays are newly introduced, each of which contains serially connected key block 6 and shift register 7. Block 6 contains the elements And 8-10, the inverter 11 and the power of OR 12. The input signal is fed to the 2nd inputs of the blocks. The signal delay is selectively changed by turning on the corresponding block 6, -6 according to the program of block 2, which contains the addresses of the points of the input signal in a predetermined and variable order. Block 2 is synchronized by block 1 for simultaneous operation by blocks 5, -5,. The selected signal is fed to the Z register. 2 Il.

I

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WITH

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This invention relates to telephone communications systems with a temporary seal.

The purpose of the invention is to increase the number of switched paths.

Figure 1 shows the structural electrical circuit of the device for temporary switching; FIG. 2 is a structural electrical circuit of the key block.

The device for temporary switching contains a synchronization unit 1, a storage unit 2, n decoders, a serial-parallel register 4, n blocks 5, -5, delays, n key blocks 6, - & n, n registers 7, -7 „ shear.

The key block contains the first 8, second 9 and third 10 elements AND, the inverter 11 and the element OR 12,

The device for temporary switching works as follows.

The input signal is supplied to the inputs of the key blocks 6, -6,. The signal delay is selectively changed by | turning on the corresponding key block 6, -6f | according to the program of the storage unit 2, which contains the addresses of the points of the input signal in a given and variable order. By sampling the input signal addresses from the storage unit 2, signals are inputted to the corresponding second inputs of the key blocks, and from the corresponding second outputs of the key blocks 6, -6 are removed.

The storage unit 2 is synchronized by the unit 1 for simultaneous operation by the blocks 5., -5fj of the delay, and the selected signal is fed to the serial-parallel register 4.

From the outputs of the serial-parallel register 4, the signal is fed to decipherors 3, -3 ", which realizes the control of switching on the corresponding key block 6, -6". When the key block 6, -6 is opened, information is recorded in the corresponding shift register 7, -7.

Key blocks 6, -6 work as follows.

The control signal is fed to the control input of the key block, to the first inputs of the second 9 and third 10 elements And when

signal at the second input of the key block 6 (-6 signal goes through the element OR 12 to the first output of the key block 6, -6ts.

At the same time, this signal prohibits the operation of the first element E8 through the inverter 11. If there is a control signal on the control input of the key block b, -6j, and a signal on its first input, the signal is output through the second, element 9 to the second input of the key block 6 , -6.

Claims (1)

Formula iso rete n i A temporary switching device comprising a serially connected synchronization unit and a storage unit, as well as n decoders, characterized in that, in order to increase the number of switched paths, a serial-parallel register and n serially connected delay blocks are entered, each of which contains serially connected key block and shift register, while the second inputs of the key blocks are interconnected, the second outputs of the key blocks are interconnected, and the control inputs are key These blocks are with the outputs of the corresponding decoders, the inputs of which are connected to the corresponding outputs of the series-parallel register, the input of which is connected to the output of the storage unit, each key block containing the first AND element in series and the OR element whose output is the output of the key block, as well as the second and third elements And, the first inputs of which are interconnected and connected to the input of the inverter and are the control input of the key block, the output of the inverter is connected to ne The first input of the first element AND is the first input of the key block, the output of the third element AND is connected to the second input of the OR element, and the code of the second AND element and the second output of the third AND element are respectively the second output and the input of the key block. Sf phi.2