SU1394448A1 - Clock synchronizer - Google Patents

Abstract

The invention relates to the field of telecommunications and radio engineering and mb used in discrete information transmission systems, in radar and radio navigation systems; The aim of the invention is to improve the synchronization accuracy with varying values of the difference in signal levels and noise. The device contains a quadrant 4, low-pass filters 6-8, multipliers 9, 10, a band-pass filter (PF) 11, a delay block 14 controlled, a generator of 16 clock pulses, a frequency divider 17. To achieve the goal, a quadratic detector 1, two blocks 2, 5 subtractors, a voltage divider 3, a controlled amplifier 12, an additional amplifier 13, and a control signal driver 15 are introduced into the device. The IF II selects a frequency range with a center frequency equal to the 2nd harmonic of the clock frequency. The exact selection of the 2nd harmonic is performed by a PLL loop containing multiplier 10, controlled amplifier 12, filter 6 and controlled oscillator 16. Min. The mean square tracking error q for a given S / N ratio m. obtained by the optimal choice of the structure of the filter 6 and the coefficient. amplification of amplifier 12 in the tracking loop, and the type of filter 6 depends on the correlation of the St-in signal, and the coefficient. the gain is mainly a function of the S / N ratio. 2 Il. с (Л О5 со i4 ф 4 00

Description

The invention relates to telecommunications and radio engineering and can be used in discrete information transmission systems, radar and radio navigation systems.

The purpose of the invention is to improve synchronization accuracy with varying levels of signal and noise.

FIG. Figure 1 shows the structural electrical circuit of the clock synchronization device; in fig. 2 is an autocorrelation function of a sequence of binary pulses of arbitrary shape.

The clock synchronization device contains a quadratic detector 1, the first block 2 of subtraction, the divider of 3 voltages., Quad 4, the second block

59 readings 5 first 6, second 7 and third 8 low-pass filters, first 9 and second 10 multipliers, band-pass filter 11, controlled 12 and additional 13 amplifiers, delay block 14, driver 15 of the control signal, controlled oscillator

16 clock pulses and frequency divider 17.

The clock synchronization device operates as follows.

An input signal representing a sequence of binary pulses of an arbitrary (random) form with a fluctuating clock frequency f

and additive broadband noise,

multiplied with its copy shifted by half the duration of the clock frequency period in the first multiplier 9 (Fig. 1). As a result, a clock frequency harmonic appears in the spectrum of the signal at the output of the first multiplier 9.

The band-pass filter 11 is in the ET region of frequencies with a center frequency equal to the second harmonic of the clock frequency. The second harmonic is precisely separated by a PLL loop containing a second multiplier 10, a controlled amplifier 12, a first filter

6 and a controlled oscillator 16. The minimum standard error of tracking q for a given signal-to-noise ratio can be obtained by optimally selecting the structure of the first filter 6 and the gain of the controlled amplifier 12 in the tracking loop, and the type of the first filter 6 depends on the correlation properties signal, and the gain is in

mainly on the ratio value. cash / noise

To analyze the parameter q, certain properties of the autocorrelation functions of binary signals are used. With a non-redundant encoding, the autocorrelation function has the form shown in FIG. 2. The following relationships are true:

B (0) 2B (|); (one)

(s (t) - (s (t) r

12)

(S (t) -S (t)). (S (|) -S (|), X)

where BC is the autocorrelation function of the binary signal S (t); T is the clock repetition period .J. (the bar above the symbols is the averaging sign

on time)

At the output of the quadratic detector 1, a signal of the form

(V)

with 2 c. f i t

(four)

 t o g

-printed signal;

-White noise;

-power noise.

From (4) it follows

g - - 2 B. J. X r2

t

t t

Considering the proportions

(1) (5) (3),

r: t

S 23 (5 - (S (t)) 2S (t) S (t - |) +

(t)) (6)

Then from (5). Get

g

0

; e xj-2s (t) s (t + i) + (s (t)) (7)

The last term in the right part (7) is formed using the second filter and Quad 4, the second term in the right part (7) is formed using the delay block 14, the first multiplier 9, the third filter 8 and the additional amplifier 13. In this case the gain of the additional amplifier 13 is equal to two, and the delay unit 14 is automatically adjusted to the value T / 2 by means of the driver 15. The average power of the useful signal according to (6) is formed at the output of the second unit 5

subtraction, and the noise power in accordance with (5) and (7) - at the output of the first subtraction unit. Relationship The signal to noise q is implemented at the output of the divider 3, which allows for the optimal tuning of the controlled amplifier 12 at the control input. While the noise present at the output of the first multiplier 9, due to their uncorrelated on the Intert at the output

vale

g minimized

of the third filter 8 and do not participate in the formation of the functions included in expression (6).

The delay unit 14 and the first multiplier 9 are simultaneously used for two purposes: to form an autocorrelation function at T

dp is the second harmonic recovery in the signal spectrum, which is followed in the PLL loop.

Claims (1)

Invention Formula A clock synchronization device containing series-connected the delay unit, the first multiplier and the band-pass filter, the first low-pass filter connected in series, the controlled clock generator and the second multiplier, as well as the quad, the second and third low-pass filters and the frequency divider, characterized in that - o five 0 five 0 g synchronization at varying values; No signal and noise levels, the first subtraction unit, the voltage divider and the controlled amplifier, the information input and output of which are connected respectively to the output of the second multiplier and the input of the first low-pass filter, connected in series with the additional amplifier and the second a subtractor unit, the output of which is connected to the second inputs of the first subtraction unit and voltage divider, as well as a driver of the control signal, the output of which is connected to the control unit at the output of the second lowpass filter via a quad is connected to the second input of the second subtraction unit, the output of the first multiplier through the third lowpass filter is connected to the input of an additional amplifier, the output of the controlled clock generator is connected to the inputs of the frequency divider and the control signal generator, the output of the bandpass filter is connected to the second input of the second multiplier, and the input of the quadratic detector is combined with the input of the second filter of the lower Frequency, the second input of the first multiplier, and the information capture of the delay unit, the second input of the first multiplier and the output of the frequency divider are the input and output of the device, respectively. -G g / g about t / 2 t Futz  g