SU902287A1 - Device for measuring clock frequency of pseudorandom sequence - Google Patents

Description

The invention relates to radio engineering and can be used in data transmission systems, radar, communications and other systems.

Known measuring device clock rate pseudorandom sequence post- ⁵ (CAP) comprising a multiplier connected in series, a bandpass filter and synchronous detector, and a phase detector connected in series, a filter ^10, a lowpass tunable delay line and discrete unit delay, to which the second input and the output of the phase detector is connected to the output of the switching signal generator, the third input of the discrete delay unit is connected directly to the output of the low-pass filter, while the input eremnozhitelya and second input perestra- ivaemoy _m delay lines connected to each other through a tunable delay line connected to the second input of the multiplier [f].

However, the known device has a relatively low measurement accuracy.

The purpose of the invention is to improve the accuracy of measurement.

This goal is achieved by the fact that a filter limiter and additional series multiplier and a band-pass filter are connected in a known device, the output of which is connected to an additional input of a synchronous detector, the output of which is connected through a filter limiter to the input of a phase detector, the first input of an additional multiplier is connected to the output tunable delay line, the second input is connected to the output of the discrete delay unit, the fourth input of which is connected to the second input second delay line.

The drawing shows a structural electrical diagram of the proposed device.

The pseudo-random sequence clock frequency measuring device comprises a multiplier 1, a bandpass filter 2, a synchronous detector 3, a filter limiter 4, a phase detector 5, a lowpass filter 6, a tunable delay line 7, a discrete delay unit 8, an additional multiplier 9, an additional bandpass filter 10 and a switching signal generator 11.

. The device operates as follows.

In the synchronism mode, the PSP signals are received at the inputs of the multiplier 1, delayed one relative to the other by half the duration ^ of the PSP symbol. The delay is provided by a tunable line 7 A bandpass filter 2 from the spectrum of the resulting signal extracts the signal of the first harmonic of the clock frequency of the SRP and feeds it to the input of the synchronous detector 3 · The signal delayed relative to the input by 0.5 in the tunable line 7 and at the second input of the additional multiplier 9, the SRP signal is supplied from the output of block 8, which, under the action of a switching signal of the meander type generated by the generator 11, connects the second input of the additional the body multiplier 9 is alternately either with the input of the device or with the ₃₅ output of the delay line of block 8. As a result of switching one of the multiplied SRPs, the signal of the first harmonic of the clock frequency at the output of the additional band-pass filter 10 turns out to be phase-0-manipulated; 180 °.

At the output of the synchronous detector 3, a signal corresponding to the switching law is selected, the phase of this signal depends on how much the delay in the tunable band corresponds to tunable line 7 and block 8 of duration L _v , the bandwidth symbol. The output of the phase detector 5 produces a signal whose amplitude is proportional to the phase shift of the signals at its inputs. This signal after filtering in the filter 6 is fed to the corresponding inputs of the tunable line 7 and block 8, setting the delay in them in synchronism mode at 0.57c received SRP. Measurement of the clock frequency of the SRP can be performed using signal 5 from the output of the bandpass filter 2 or from the output of the filter 6.

The proposed device allows to increase the accuracy of measurements of the clock frequency of the memory bandwidth with the same ratio of 10 signal to noise output.

Claims (1)

The invention relates to radio engineering and can be used in data transmission systems, radar systems, communications and other systems. A device for measuring a pseudo-random sequence (PSP) Frequency Frequency is known; the output of the switching signal generator is connected, the third input of the discrete-delay block is connected directly to the output of the low-pass filter, and the input is not The multiplier and the second input of the tunable delay line are interconnected and connected via a tunable delay line to the second input of the multiplier tj. However, the known device has a relatively low measurement accuracy. The purpose of the invention is to improve the measurement accuracy. This goal is achieved by introducing a filter limiter and an additional multiplier connected in series and a band-pass filter to a known device, the output of which is connected to the additional input of a synchronous detector, the output of which is connected through the filter limiter to the input of the phase detector, the first input of the additional multiplier is connected to the output of the tunable delay line, the second input is connected to the output of the discrete delay block, the fourth input of which is connected to the second input of the rearrange delay line. The drawing shows the structural scheme of the proposed device. 3 A pseudorandom sequence clock frequency measurement device contains multiplier 1, band-pass filter 2, synchronous detector filter-limiter, phase detector 5, low-pass filter 6, tunable delay line 7, discrete-delay block 8, additional multiplier 9, additional band filter 10 and the generator 11 of the switching signal. The device works as follows. In synchronism mode, the PSP signals are received at the inputs of the multiplier 1, delayed one relative to the other by half the duration T of the PSP symbol. The delay is provided by a tunable line 7 By a band filter 2, the signal of the first harmonic of the SRP clock frequency is extracted from the spectrum of the resulting signal and fed to the input of the synchronous detector 3. and to the second input an additional multiplier E supplies the signal of the SRP from the output of block 8, which, under the action of a switching signal of the type square, formed by the generator 11, connects the second input additional ADDITIONAL multiplier 9 alternately to the input device, the output of the delay line unit 8. As a result of switching one of the SRP signal peremno zhaemyh first clock harmonics at the output of an additional bandpass filter 10 It appears keying of phase O; 180. At the output of the synchronous detector 3, a signal is selected that corresponds to the switching law, the phase of this signal depends on how closely the memory bandwidth delay in the tunable line 7 and block 8 corresponds to the duration and, the memory band symbol. At the output of the phase detector 5, a signal is generated, the amplitude of which is proportional to the phase shift of the signals at its inputs. After filtering in filter 6, this signal is applied to the corresponding inputs of the tunable line 7 and block 8 to set the delays in them in synchronism mode by 0.5 received SRP. The measurement of the clock frequency of the memory bandwidth can be performed using a signal from the output of the bandpass filter 2 or from the output of filter 6. The proposed device allows improving the accuracy of measuring the clock frequency of the memory bandwidth at the same signal-to-noise ratio at the output. Claims. A pseudo-random sequence (PSP) clock frequency measuring device containing serially connected multiplier, band-pass filter and synchronous detector, as well as serially connected phase detector, low-pass filter, tunable delay line and discrete delay block, to the second input of which and the phase detector input the output the generator of the switching signal, the third input of the discrete-delay block is connected directly to the output of the low-pass filter, and the input multiply The customer and the second input of the resettable delay line are interconnected and are connected via a tunable delay line to the second input of the multiplier, in order to improve the measurement accuracy, a filter limiter and a serially connected additional multiplier and band pass filter are connected. to the additional input of the synchronous detector, the output of which through the filter limiter is connected to the input of the phase detector, the first input of the additional multiplier is connected to Exit tunable delay line, a second input connected to the output Tr rtnoy delay unit, the fourth input of which is connected to the second input of the tunable delay line. Sources of information taken into account in the examination 1. USSR author's certificate. No.-, cl. H 04 L 7/02, 1977 (prototype). Lj  V r