SU1394444A1 - Digital signal receiver - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the reliability of receiving information by eliminating slippage. The device contains a block of 1 input registers, a block of 2 memories of input information. The channel definition block 3, the comparison block 4, the output information memory block 5, the address counter 6, the output register block 7 are entered. Block 3 co. holds zl-t NOT, two el-AND, two el-OR, memory block, register. Block 4 contains zl-t comparison and el-tI. Block 5 contains two zl-that AND, el-OR, memory block, register. Counter 6 contains two triggers, two zl-ti OR, four e-ti I. Block 7 contains six e-ti I, two shift registers, e-ti OR. The device provides synchronization of digital channels and eliminates slippage over the duration of a telephone call of il6 hours. This duration can be obtained by using quartz g-waves having relative instability K 1-10 9 silt. "(L

Description

her co 4 4 j

four

The invention relates to communication technology and can be used in digital switching systems.

The purpose of the invention is to increase the reliability of receiving information by eliminating slippage.

Fig. 1 shows a block diagram of a device for receiving digital signals; figure 2 | 0 block input registers; FIG. 3 shows an input information storage unit; 4 shows a channel detection unit; Fig. 5 shows an output memory block; figure 6 is the address counter; 15 in Fig. 7 is a comparison unit; on Fig - block output registers; figure 9 - cycle paths.

A device for receiving digital signals (FIG. 1) contains a block 1 20 of input registers, a block 2 of input information memory, a block of channel definition 3, a block 4 of comparison, a block of 5 output memory, a counter 6 of address, a block of 7 output registers 25 ditch

Block 1 input registers (figure 2) contains the first, second 1-2, third i-3 and fourth 1-4 elements And, the first 1-5 and the second 1-6 shift registers 30, the fifth 1-7 and sixth 1 -8 elements AND, element OR 1-9, counter 1-10, pulses, first trigger 1-11, seventh element AND 1-12, second trigger 1-13 and eighth element AND 1-14. 35

Block 2 of the input information memory (FIG. 3) contains the first 2-1 and second 2-2 elements AND, the OR element, block 2-4 of the memory and register 2-5.

the shift, the fifth 7-7 and the sixth 7-8 elements AND and the element OR 7-9.

A device for receiving digital signals operates as follows.

Switched information signals and transmitted in the digital channels of the paths PCM-30/32 or PCM-120/128 are fed to the input of the first 1-1 and fourth 1-4 elements AND Fig.2 of block 1 of the input registers (figure 1). Together with the information in block 1 of the input registers also receives the clock frequency f. of the incoming line and the pulses t, which determine the numbers of the time channels of the PCM-30/32 paths and enter the input of the counter 1-10 of the first /. trigger 1-11. Using these pulses, the counter 1-10 determines the address (number) of the temporary channel through which the next digital PCM signal arrives. Address A from the output of counter 1-10 is provided to the inputs of blocks 2-4 (Figures 1 and 2). The signals y and f from the low-order trigger output of counter 1-10 control the operation of the AND 1 -1 -1-8 elements. In this case, PCM signals arriving in odd channels (1.3, .. o, 31-) are transformed from a serial code into a parallel code using a shift register 1–5, and those arriving in even channels (0.2, 4, .. ,, 30) - using register 1-6 shift. The signal t provides the conversion of PCM signals using shift register 1–5 and outputting the previously converted signal from the output of the second register 1–6 shift through

Channel definition block 3 (Fig. 4) element 40 AND 1-8 and element OR 1-9 do not contain element 3-1, pervy 3-2, block 2 input. Signal ji provides

similar operations performed using the second register 1-6 shift.

and the second 3-3 elements AND, the element OR OR 3-4, the memory block 3-5 and the register 3-6.

Comparison unit 4 (Fig. 7) contains 5 element 4-1 comparison and element 4-2.

The output memory block 5 (FIG. 5) contains the first 5-1 and second 5-2 elements AND, the element OR 5-3, the block 5-4 of memory, the register, 5-5.

The address counter 6 (FIG. 6) contains the first 6-1 and second 6-2 triggers, the first 6-3 and the second 6-4 OR elements, and the four AND 6-5 elements - 6-8. ,

Block 7 output registers (Fig.8) contains the first 7-1, the second 7-2, the third 7-3 and the fourth 7-4 elements And, the first 7-5 and the second 7-6 registers

50

element AND 1-7 and element OR 1-9. The information and the clock frequency f are fed to the first shift register 1-5 through the elements 1-1 and 1-2, and to the second shift register 1-6 through the elements 1-4 and 1-3.

The recording of information from block 1 of the input registers into block 2 of the memory of the input information is provided by the Record signal (GTP) generated by the triggers 1-1 and 1-13 and And elements 1-12 and 1-14. In this case, at the instants of accumulation time in block 1 of the input registers of the next PCM signal, the trigger 1-11 is set to state 1

the shift, the fifth 7-7 and the sixth 7-8 elements AND and the element OR 7-9.

A device for receiving digital signals operates as follows.

Switched information signals and transmitted in the digital channels of the paths PCM-30/32 or PCM-120/128 are fed to the input of the first 1-1 and fourth 1-4 elements AND Fig.2 of block 1 of the input registers (figure 1). Together with the information in block 1 of the input registers also receives the clock frequency f. of the incoming line and the pulses t, which determine the numbers of the time channels of the PCM-30/32 paths and enter the input of the counter 1-10 of the first /. trigger 1-11. Using these pulses, the counter 1-10 determines the address (number) of the temporary channel through which the next digital PCM signal arrives. Address A from the output of counter 1-10 is provided to the inputs of blocks 2-4 (Figures 1 and 2). The signals y and f from the low-order trigger output of counter 1-10 control the operation of the AND 1 -1 -1-8 elements. In this case, PCM signals arriving in odd channels (1.3, .. o, 31-) are transformed from a serial code into a parallel code using a shift register 1–5, and those arriving in even channels (0.2, 4, .. ,, 30) - using register 1-6 shift. The signal t provides the conversion of PCM signals using shift register 1–5 and outputting the previously converted signal from the output of the second register 1–6 shift through

element AND 1-7 and element OR 1-9. The information and the clock frequency f are fed to the first shift register 1-5 through the elements 1-1 and 1-2, and to the second shift register 1-6 through the elements 1-4 and 1-3.

The recording of information from block 1 of the input registers into block 2 of the memory of the input information is provided by the Record signal (GTP) generated by the triggers 1-1 and 1-13 and And elements 1-12 and 1-14. In this case, at the instants of accumulation time in block 1 of the input registers of the next PCM signal, the trigger 1-11 is set to state 1

3 1394444 using a pulse arriving at

ko lo lo eir tc uv bli kro lo lo

input counter 1-10. Then, using the signal Read (THU) from the counter 6 of the address, through the element 1-12, the trigger 1-13 is set to state 1, which allows the element 1-1.4 to open and skip the signal of the RFP coming from counter 6 addresses following the THU signal. The signal of the RFP sets the trigger 1-11 to the state O, and then the signal THU using the element I 1-12 sets the trigger 1-13 also to the state O.

With the help of the signal ZP, information is recorded from the block 1 of the input registers into the block 2-4 of memory using the elements AND 2-1 and OR 2-3. In this case, the address A of the memory cell into which the information is written comes from block 1 of the input registers through the elements AND 2-1 and OR 2-3.

Information is recorded in the channel definition block 3 only at the time of establishing connections. At the same time, the address A of the time channel of the PCM-30/32 track, which is used in the switching system (CS) of the station during the connection establishment process, goes from the CS to the input of the comparison unit 4; on the other input of which receives the same address from block 1 of the input registers. If using the comparison element 4-1 (FIG. 7 it is established that these addresses A are the same), then from the output of the comparison element 4-1, the signal oj is sent to the AND 4-2 element which passes the signal of the RFP transmitted from block 1 of the input registers to the block 3 definitions of channels. In this case, the information AND, which is the address A of the temporary channel that is currently being serviced by block 11, is recorded in the corresponding cell of memory block 3-5 (Fig. 4).

The address A of the memory block 3-5, to which information is recorded, comes from the counter 6 of the address c; .. trigger 6-1 (Fig. 6). In this case, the high-order bit f of this address A is inverted with the aid of the element HE 3-1 (FIG. 4). Then the address A comes through the elements AND 3-2 and OR 3-4 to the input of the memory block 3-5. Thus, the address A, due to the inversion of its high-order bit, differs from the address of the counter 6 by half of the T 125 cycle of the ISS of the PCM-30/32 path.

0

about -

Blocks 2,3 and 5 of memory have the same number of memory cells, equal to the number of digital channels served. The number of memory cells is 32, if these blocks serve one, the PCM-30/32 path. As the number of paths increases, the number of cells increases proportionally. The numbers of memory cells, blocks are the same. These memory cells serve the digital channels of the PCM-30/32 path assigned to them. The memory cells of the channel definition block 3 and the memory block 5 of the output information are counted with the help of the counter 6 of the address, which then generates the address A of the link and the signal THU (fig.b).

All recording signals (ZP, ZP) and

0 reading (THU, THU, THU) is generated with the help of trigger 6-2, elements OR b-3 and 6-4, and elements AND 6-5 - 6-8 (Fig.6). The generation of these signals is carried out using a clock.

5 frequencies f (- work of the CS and the station as a whole. Thus, all the units of the device, except block 1 input registers, work synchronously with the work of the CS and the station.

When reading information from ka 3 definitions of channels, the address .. A, coming from counter 6 of the address, passes through the elements AND 3-3 and OR 3-4 due to the signal THU, and is fed to the input of memory block 3-5 (Fig.A) The readout is carried out by the TH signal, whereby the read information, which is the address A of the time channel (memory cells of blocks 3 and 5) and is used to rewrite the switched signal from block 2 to block 5, is written to-register 3-6 and stored in it until the next read operation. Similarly, the output from the block is 5. With the help of the THT signal. At that, the address A, coming from the address counter 6, passes through the elements AND 5-2 and OR 5-3 to the input of the memory block 5-4. The read information is recorded in register 5-5 (FIG. 5) and is input to the block of outgoing registers 7. Information is read from block 2 of the input information produced by the signal THU with the help of address A coming from block 3 of the channel definitions. and. OR 2-3 and enters the input of the block 2-4 memory

five

0

0

five

(fng.Z). The read information is recorded in register 2-5 and stored in it until the next reading by the CTG signal. The information is rewritten from block 2 to block 5 by the Signal RFP signal using the address A from block 3. At the same time, the address A passes through a "- cut And 5-1 and OR 5-3 elements and is fed to the input of the memory block 5-4, providing the recording of information from the block 2 of the memory of the input information by the signal of the RFP, (figure 5).

The information coming from the output memory block 5 to the block

7 output registers are converted in block 7 from a parallel code to a serial one and provided to the switching system of the station in synchronous channels. The conversion of MKM signals is carried out using the shift registers 7–5 and 7–6. Shift registers are controlled by signals of

and 0, coming from the output of the trigger 6-1 of the lower order bit address of the temporary channel of the address counter 6 (FIG. 6). At the same time, information from the information storage unit 5 is fed to the shift register 7-5 through the AND 7-1 element using the signal c /. At the same time, using the signal of, passing through the AND 7-4 element the clock pulses fj, shift the PCM signal bits along the register 7-6 and output them through the AND 78 and OR 7-9 elements in the CS. Similar operations are carried out under the control of the signal d, which with the aid of the AND 7-3 element provides reception of information to the shift register 7-6 and with the aid of the AND 7-2 element and the shift register 7-5 ensures the output of information from this register through the elements Both 7-7 and OR 7-9 to the output of the device, which then synchronously with the work of the station enters the CS.

Slippage is eliminated as follows.

Suppose a station establishes a connection between subscribers using a CS. It uses the 1st 3rd time channel of the PCM-30 / / 32 path, which is served by the proposed digital channel synchronization device. Then from the CS to the input of unit 4 of the comparison receives the address A 01101 of the 13th temporary channel. This address is issued from

0

five

0

five

0

five

0

five

CS during one cycle of T 125 μs of work of IKM-30/32 paths, i.e. is located at the input of block 4 of the comparison unit for 125 µs. Since the block 1 of the input registers operates at the frequency of the incoming communication line, and the oc-i tal blocks of the device - at the frequency fj, the station, these frequencies may differ from each other. Therefore, the 13th channel address A 01101 from block 1 of the input registers can be received at the input of the comparison block 4 at any time during cycle T, for example, when address A 6 of the 30th time channel is found (Figure 9). Then the comparison unit 4 outputs to the input of the determination unit 3. channels, the signal of the RFP, which is written to the memory cell with the address A 14 (01110) information AND 01101, i.e. address of the 13th temporary channel (). The memory cell number A 14 (01110) of memory block 3-5 (FIG. 4), in which information AND 0110 is recorded from block 1 of the input registers, is obtained from the number A 30 (ill 10} due to inverting with the help of the HE element 3 -1 of the higher bit of the address A 11110 (-Fig.9, the T cycle of the operation of the PCM-30/32 paths is shown in the form of a ring divided into 32 time channels).

Thus, at the time of establishing the connection, the information of the 13th temporary channel (01101) is recorded in block 2 of the input memory at times when counter 6 has address A 30 (lllO), and is read from block 2 and overwritten block 5 of the memory of the output information at the moments of time when the address A 14 (01110) is present on the counter 6 of the address, i.e. later on the polite, the fault cycle T of the operation of the paths PCM-30 / / 32: T 0.5 T (Fig.9). Here, the time period T is used to eliminate the slip.

The difference between the frequencies fd and fc can be positive and negative (Fig.9):

t / sf l - f s- (O

Relative instability of generator station equipment

one

K, (- -i -) / - i-

 dt / t

L

(2)

7 13944

The time interval Z5t transfer information between two PBXs, during which there is a mismatch in the transmission, equal to one bit.

 (3)

& t 1 / K-f.

Duration of telephone conversation without proskalzyuani

Lm -at

4M is the number of information bits transmitted during the interval (interval) of time DT.

The value of & M can be determined by:

10 (4)

4M

LT - f

By reading (3) and using formula (4), we obtain

tp 4T / K,

The resulting expression (6) takes into account the linear drift of its own hour

the connected input register block, the information input and the input of information pulses, which are the corresponding inputs of the device for receiving digital signals, and the input information storage unit, characterized in that, in order to test the reliability of the information received by eliminating slippings, the address counter, the first, second and third outputs of which are connected respectively to the write and read input of the block,. input registers and the input of the input information memory block, the comparison unit connected in series, the first address input and the recording entry of which are connected to

20 corresponding to the inputs of the input information memory block and are connected to the second and third outputs of the input registers block, and the channel definition block, the first address input of which

25 is connected to the corresponding input of the comparison unit, connected in series to the output information storage unit, to the first address input and whose information input is under

then you. In this case, the random component 39 is connected respectively to the second address fluctuation (linear jitter) is usually suppressed in the linear equipment of the transmission system.

Using formula (b), one can determine the duration of a telephone call without slipping for T 0.5T and K 1-10-. This duration h.

Thus, the proposed device is very effective, as it allows to synchronize digital channels and eliminate slippage during a telephone conversation tp-16 hours. This duration can be when using quartz oscillators having a relative instability K 1 -10 .

Claims (1)

Invention Formula A device for receiving digital signals comprising 35 40 45 50 the input input of the memory of the input information and the output of the channel detection unit, the output of the memory of the input formation and the block of output registers, the second input of which is connected to the first input of the address counter and is the input of the switching frequency signal of the switching system; the addresses and the second address input of the comparison unit are the corresponding inputs of the switching system, the fourth and fifth outputs of the address counter are connected respectively to the write input of the output information memory unit and the inputs with The reading unit of the channel definition block and the output memory block, to the second address inputs of which the corresponding outputs of the address counter are connected, and the corresponding output of the address counter, are connected to the control input of the code registers. the second address is connected accordingly the input input of the memory of the input information and the output of the channel detection unit, the output of the memory of the input formation and the block of output registers, the second input of which is connected to the first input of the address counter and is the input of the switching frequency signal of the switching system; the addresses and the second address input of the comparison unit are the corresponding inputs of the switching system, the fourth and fifth outputs of the address counter are connected respectively to the write input of the output information memory unit and the inputs with The reading unit of the channel definition block and the output memory block, to the second address inputs of which the corresponding outputs of the address counter are connected, and the corresponding output of the address counter, are connected to the control input of the code registers. ftsffjt.l E. Nzbl Izb.5 Schig.Z MySji.5 fig Ma dl.5 aL. ffjif / t, 3 1- 3ffJr.5 ftsS / f.S THU FIG. five ff W (Ch1 wlg m ff3ff 2 5-5 vd / .7 ZPG sn in .J.6 Sffj}. P g4. 6-1 -; T L ffsdjf.r From cop sn ff3S / r.6 7-r t Z ffsSJf.S d From / (With fc. 7-3 7-4 1394444 ZP / Ti t / T CV one I 5-j 6-4 J / 7 vr, r -five 6-6 6-7 6-8 GM 6-2 5-f 6-2 t f / 7. fa 7 8 / fC CputB (OnDJ) , 75 eleven FIG. 9 V / .5Г