SU526939A1 - Device for transmitting and receiving discrete information - Google Patents

Description

The closest to the invention in technical essence and the achieved result is a device for transmitting and receiving information, containing a chronizer, the output of which is connected to the clock input of the parallel code into a serial code, a trigger, the single input of which is connected to the first input of the device and the starting input of the pair converter; Relay to serial, serial to parallel, first, second, third, and fourth line converters, with a group of inputs and groups sootvetstveppo output devices are connected to data inputs of the converter parallel to serial converter and the data outputs serial to parallel.

A disadvantage of the known device is the low throughput due to the impossibility of simultaneously transmitting several signals from the receiving side to the transmitting one and the impossibility of simultaneously transmitting signals from both sides.

The purpose of the invention is to increase the capacity of the device.

This is achieved by the fact that the proposed device comprises a sealing unit and a control signal separation unit, the first, second, third and fourth elements "H", element "LII, elements" AND-NOT, and the first inputs of the first and second elements "And are connected to the outputs of the parallel code to serial converter, the second inputs of the first and second I elements with the second input of the device, and the outputs of the first and second I elements through the first and second communication lines are respectively connected with the first and second inputs of the converter sequence code in parallel with the input element "or and" AND-NOT. The serial output of the serial to parallel converter, the outputs of the elements "OR," AND-NO, through the third element "AND are connected to the third input of the converter of the serial code to the parallel, the fourth input of which and the first input of the control signal compression unit, the fourth and fifth inputs of which are connected respectively to the second and third inputs of the control signal compression unit, the first and second outputs of which are connected via the third and fourth communication lines respectively of the first and second separation unit inputs the control signals, a first output connected to a first input of the fourth elemepta "And, the second input of which is connected to the trigger output unit. The output of the OR element, the second output of a serial-to-parallel converter, the second and third inputs of the separation unit control their signals are connected to the first, second, third and fourth outputs of the device, the fifth output of the device is connected to the output of the fourth And element, and zero trigger input — with third line of communication.

The drawing shows a block diagram of the proposed device.

The circuit contains a chronizer 1, a parallel code-to-serial converter 2, a serial code-to-parallel converter 3, a control signal separation unit 4, a control signal multiplexing unit 5, a trigger 6, elements "AND 7-10, an element" OR 11, an element " AND-NO 12, the elements “AND 13, 14, the elements“ OR 15-21, inputs 22-27, outputs 28-33, first, second,

the third and fourth lines of communication 34-37, respectively, and the elements And 38, 39.

The device is intended to transmit the signals of the C 3 junction (GOST 18146-72) to a small number of communication lines and restore them to the receiving side.

In the description, the following signal conventions are accepted: GI - source readiness, TI - source control, GN - receiver readiness, UT - receiver control, OSH - error, DN - source data.

The hacker 1, the parallel code to 2 serial code converter 2 and the elements “And 7, 8 are intended for signal compression

source of information and their transmission. The control signal separation unit 4 serves to separate the information user signals (G; P, VN, OSH) transmitted via communication lines 36, 37. Trigger 6 and element “AND 9

delaying the leading edge of the LV signal until the termination of the MD signal.

The element "OR 11 and the element" AND-NO 12 serve to separate the GI signal and the signals

synchronization, transmitted by communication lines 34, 35. Serial-to-parallel converter 3 converts the source data into a parallel code and generates an MD signal. Seal block 5

control signals can be performed, for example, in the form of definitely connected elements "And 13, 14 and elements" OR 15, 17, block 4 of the separation of control signals - in the form of elements "OR

18-21 and the elements 38-39. The converter of the consecutive code to the parallel code is a shift register by n + 1 bit, where n is the length of the words to be converted.

The device works as follows. At the input to the signal UI 22, the data of the source DI is entered through a group of inputs 27 into the converter 2 and then is output in successive cycles for 5 cycles.

code with an active zero to the inputs of the elements "And 7, 8. These signals must be pulsed and inverted, i.e. when issuing a single value of the data element at a single output of the converter 2 must

be a negative (or zero) impulse,

The second inputs of the elements "And 7, 8 receive the input GI at the input 23, therefore the elements" And 7, 8 maintain the level of the logical unit in the communication lines 34, 35 and the time of the existence of the signal GI, except for the moments of transfer of the data elements from the converter 2 Since the zero and one data element mappings are mutually exclusive, the level of the logical unit in the communication lines 34, 35 is not interrupted during data transmission at the same time. At the output of the element "LII 11, the signal coincides with the signal GI at the outputs of the elements" And 7, 8. At the output of the element "AND-NOT 12, the signal is formed at zero signals in any of the communication lines 34, 35, i.e. at transfer of data items. The output signals of the NAND 12 are the shift signals for the converter 3 from the serial code to the parallel code.

The inverter 3 is set to its initial state in the absence of a UE signal from the information consumer (in the intervals between successive VL signals). At the input of the transducer p pulses at its outputs 28 a parallel code of this source is set, and at this time the leading edge of the signal UI is formed. This state of the converter is maintained until the UE signal is removed at the input 24 by the information consumer.

Thus, all information source signals (CI, CI, CI) are transmitted over two wires. The sigals GN, UNH, OR, arriving at the inputs 24-26 from the consumer of information, are combined by block 5 and transmitted to the communication lines 36, 37.

The GN signal is transmitted by the level-logic of the logical unit in both lines 36, 37, the signal by the UN is inverted by this level in one predetermined, for example, communication line 36, the OR signal in the other communication line 37. When transmitting the OR signal, the interruption is prohibited a single level along the transmission line of the signal UN, to exclude simultaneous interruption in both lines 36, 37.

By block 4 of the control signal section, the GN, CN, and OR signals are separated from the communication lines 36, 37 and are output to individual signals. The signals GI, GN and OSH on the outputs 29, 31, 32 of the device and the signal UNI fia output 33 coincide in time with the corresponding signals on the inputs 23, 25, 26 of the device.

The average output signal of the MD at the output 30 and the source data at the output 28 of the device is delayed relative to the corresponding input signals at the time of transmission of the source data by a serial code on the communication lines 34, 35. Such a delay does not violate the exchange discipline on the SOC connection, since the delay of these signals relative to the leading edge of the signal UND is not limited.

The leading edge of the signal UI at the output 30 of the device is ahead of the leading edge of the signal UI at the input 22 (at the output 30 it

coincides with the trailing edge of the signal UN. On input 22, it is formed by the source of information after the removal of a signal from a CN with an arbitrary delay). This may result in the consumer of information putting a signal to the UE (request for a new sign), and he can enter the source of information before he removes from the input 22 the UI signal on the previous word, which is not allowed by the exchange discipline on the NW interface.

To avoid such a situation, the device contains a trigger 6 and the element "AND 9. The trigger 6 is set to the zero state when the consumer UH signal 24 is removed from the input 24, and

in one - when the signal is removed from the UI source. The signal at the single output of the trigger 6 permits the passage of the UE signal to the output 33 of the device, i.e., only after the source signal is removed from the 22 signal of the UI.

If the OSH signal does not coincide with the UE signal (for example, it is transmitted from the end of the previous one to the beginning, 1a of the next UE), then the elements "OR 17 and 21 should be excluded.

In the converter 3 of the sequential code in parallel, the operations of information shift and pulse counting are combined. Converter 3 operates as follows. In the absence of a UN signal, the shift register is reset, the first bit being set to one, the rest to zero.

Element "And 10 permits the passage of shift pulses from the output of the element" AND-NOT

12 to the shift register until the last trigger is switched to one state, i.e., until the unit, when set to the first bit, moves to the last bit. By this time, all information bits are located in the shift register. The signal at the unit output of the last bit of the shift register indicates the end of the conversion and is used as a source control signal (MD).

The proposed device makes it possible to transmit and equivalently convert all the siali of the joint of the SOC by four wires. In this way, the information exchange discipline for the source and the consumer does not change.

The introduction of the elements H 7, 8 allows the potential signal (GI) to be transmitted together with the elements of the word and the synchronization signals. The difficulty in the joint transmission of these signals is. what some

time points omi exist simultaneously. Thus, the elements of the word must be transmitted during the existence of the GI signal. Blocks 4 and 5 provide for the transmission and recovery of two potential consumer signals (YY1, UN, OSH) on two lines of communication. overlapping in time.

The nastrosis of the device and the scarlet number of elements create a high reliability of the device. The distance and data rate is determined by the types of communication lines and

elements used in the device. In this case, no more than one pulse is spent on the transmission of each signal of the SZ junction, which provides a much higher transmission rate compared with the known device.

In addition, the proposed device has a higher bandwidth due to the fact that it does not require the transfer of start and stop signals in each parcel (which is typical of the known device), therefore the time spent on the transmission of these parcels can be used to transmit information; transmitting clock signals from the transmitting side to the receiving side, which makes it possible to transmit data elements at high speed. The speed in this case is limited only by the speed of the element base of the device.

Transmission at a bit rate per second is practically possible. When transmitting telegraph parcels, the transmission rate according to the CCITT recommendation is set to 50, 100, 200 baud.

Claims (1)

Invention Formula A device for transmitting and receiving discrete information containing a clock, the output of which is connected to the clock input of a parallel code to serial converter, a trigger, a single input of which is connected to the first input of the device and the trigger input of a parallel code to serial converter, a serial to parallel converter, the first, the second, third and fourth lines of communication, and the group of inputs and the group of outputs of the device are connected respectively to the information inputs of the transducer zovatel parallel to serial converter and the data outputs serial to parallel. characterized in that, in order to increase the capacity of the device, it comprises a sealing unit and a control signal separation unit, the first, second, third and fourth elements AND, the element OR, the element NAND, the first inputs of the first and second elements "And connected to the outputs of the converter parallel code to serial, the second inputs The first and second elements “And connected to the second input of the device, and the outputs of the first and second elemept“ And through the first and second lines of communication are respectively connected with the first and second inputs of the serial code to parallel converter, with the inputs of the elements “OR and“ AND-NOT , the first output of the serial to parallel converter, the outputs of the elements "OR," AND NOT through the third element "AND connected to the third input of the serial code converter in a parallel one, the fourth input of which and the first input of the control signal compression unit are connected to the third input of the device, the fourth and fifth inputs of which are connected respectively to the second and third input of the control signal compression unit, the first and second outputs which through the third and fourth line of communication are connected respectively with the first and the second inputs of the control signal separation unit, the first output of which is connected to the first input of the fourth And element, the second input of which is connected to the single output of the trigger, the output of the element "OR, the second output of the serial to parallel converter, the second and third outputs of the control separation unit are connected respectively to the first, second, third and fourth outputs of the device, the fifth output of the device is connected to the output of the fourth And element, and the zero input of the trigger is connected with the third line of communication.