GB1597835A

GB1597835A - Error detection arrangements for line transmission systems

Info

Publication number: GB1597835A
Application number: GB3224577A
Authority: GB
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1978-04-25
Filing date: 1978-04-25
Publication date: 1981-09-09

Description

(54) ERROR DETECTION ARRANGEMENTS FOR LINE TRANSMISSION SYSTEMS (71) We, THE PLESSEY COMPANY LIMITED, a British Company of Vicarage Lane, Ilford, Essex, IGI 4AQ; do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to error detection arrangements - for use in line transmission systems handling digital information.

Such systems are used to transmit multiplexed PCM telephone and television signals using buried coaxial cables. A system may be up to 280 Km in length. Buried repeaters which retime and regenerate the digital signals are required at intervals which are typically 2 Km when the standard 1.2/4.4 mm coaxial cable is used. Digital signals using buried coaxial cables. A system repeaters are both transmitted over the central conductor and a typical system, therefore, comprises terminal stations at each end, intermediate power feed stations at intervals not exceeding 30 Km and up to 14 regenerators between power feed stations for each of the two directions of transmission.

The digital code used in the transmission system has to satisfy a number of requirements: a) Power and signal must be separated at each repeater and this is done by passing the digital signal through an AL coupling which stops the DC power feed current and directs it to the repeater power supply circuits. The digital signal is, therefore, coded to balance the density of positive pulses against the density of negative pulses (i.e. remove any DC component) and minimise the waveform distortion caused by the coupling.

b) Monitoring of digital error rate is very desirable at each repeater.

c) Cable attenuation increases with frequency and a code which reduces the bandwidth so as to compress the signal spectrum into a region of lower attenuation is very desirable.

A number of line transmission codes have been proposed of which the high density bipolar coding of the form known as 4B3T (4 binary codes into 3 ternary) is typical. In this coding the incoming binary stream is divided arbitrarily into words of 4 bits and each combination (there are 16) is coded into a 3 element ternary word. If all 27 combinations of ternary elements are considered there are found to be: a) 6 balanced words e.g. ±0, -0+.

b) 10 words with more positive than negative pulses, said to be of positive disparity.

c) 10 words with more negative than positive pulses, said to be of negative disparity.

d) one word, 000 without pulses.

The six balanced words can be allocated directly to binary input words whereas a pair of the remaining ternary words one of the positive and the other of negative disparity can be allocated to each of the remaining binary words. At the transmitting terminal a running sum of the words alreadv transmitted, reckoning a positive pulse as +1 and a negative pulse as -1 is made and the disparity of the next word to be transmitted selected from the pair so as to reduce the running disparity. When this is done it is found that the running disparity sum always has one of six values and the code is said to be of limited disparity.

Digital errors cause the sum to be exceeded and a known method of error monitoring is to use a left-right shift register to detect the excess counts.

The last word in d) is not required and is, therefore, not used (said to be non-allowed).

this is advantageous because it has no transitions to provide desirable retiming information at each regeneration. It can also be used for word synchronisation at the receiving terminal as 000 occurs taking the end of one word with the beginning of the next but never within word when a reasonably random input stream is transmitted.

Previously violations of the disparity in disparity limited codes have been used for error rate monitoring as described above, however, this does not allow for the use of line transmission codes which are not disparity limited and is an aim of the present invention to provide an error detection arrangement which can be used with non disparity limited line codes.

According to the invention there is provided a digital line transmission system using a line transmission code involving three or more level coded combinations for transmitting binary coded information there being more line transmission code combinations than binary code combinations, the transmission system including means for detecting and indicating the reception of line transmission code combinations which are not used for binary code combinations in which the binary coded bytes are mapped onto two sets of ternary bytes and the sets of ternary bytes are used alternately and the un-used code combinations differ for each set and the transmission system includes a receiver including two N stage shift registers, where N equals the number of bits in a ternary byte, and the first of the shift registers is arranged to receive negative line pulses and the outputs of the shift registers are applied to an AND gating field which detects the code combinations which are not used for binary code combinations.

The invention will be more readily understood from the following exemplary description which should be read in conjunction with Figs. 1 to 3 accompanying the Provisional Specification.

The principle is explained here with regard to a 3B2T (three binary to two ternary) code. One ( of a large number) of mappings is given below: Binary Ternary Code A Code B ++ 000 111 +0 001 110 ± 010 0+ 011 101 00 100 0- 100 011 -+ 101 010 -0 110 001 -- Ill 000 It will be seen that there are eight possible binary words and nine ternary words available. The ternary word 00 has, therefore, been discarded in binary code A and ± in binary code B. It is proposed to use codes A and B alternately on the line.

The mapping has been chosen so that they are as far as possible inverse thus aiding the balancing of the signal when repetitive binary input signals are applied.

The principle of error detection is that the supervisory circuit is set to look within word for the occurrence of 00 and ±. The most likely errors are single ones which change the three level signals by one level.

Marginally operative regenerators may also have a tendency either to change pulses to zeros or zeros to pulses.

Error indications will be given by the corruption of:-

About three-eighths of possible single errors should be detected in this way. Hg. 1 shows a block diagram of the circuitry required. Timing pulses TP gate the positive data pulses D+ through shift register SR+ and negative data pulses D- through shift register SR- from the transmission line. The timing pulses also pass through AND gate GT which is normally open and are divided by two in the divide by two circuit DB2. The two way clock CL is then applied alternately to NAND gates GA and GB. The other inputs to gates GA and GB give selected shift register conditions.

In normal operation gate GA monitors the shift register conditions at the ends of A words and gate GB conditions at the end of B words. A connection from the top of a shift register indicates a "1" output when the shift register cell is in the "1" state and a connection from the bottom a "1" output with a "0" condition in the shift register.

For example in Fig. 2 if a digital error occurs in an A word converting it to 00 as shown at m then all cells, of the shift register are at logic "0" at the end of the word. Gate GA operates and its output goes to logic "0". This is arranged to suppress one timing pulse from gate GT via monostable multivibrator M/s. Clock CL thereafter lags by one symbol and gates GA and GB monitor the shift register conditions halfway through the A and B words. For example at n a "00" condition occurs (correctly) due to a "0" at the end of an A word and a "0" at the beginning of a B word. This deletes a block pulse and the monitoring instant slips by one more symbol.

Similarly at p a '± cofldition has been encountered by the B phase clock when it occurs (correctly) in word A. Again a slip in the monitoring instant occurs. A fourth slip at q then restores the phasing of the monitoring pulses to normal and this condition is maintained until another digital error occurs.

The result of the above process is that a single error originates a succession of monitoring point slips until the original phasing is restored. Pulse stretcher PS is arranged to give an output pulse with its longer than the succession of slips in nearly all cases and therefore a single error output for each input error providing the intervals between errors are long enough. This condition will normally be fulfilled in line transmission systems when one error per 106 elements is the error rate of interest. The symbol slipping arrangement is necessary to ensure that the error monitor synchronises itself at system startup.

Another code proposed for digital line system is the 6B4T code. (Note: There are not enough ternary words available to limit the disparity completely in this code). In this the incoming binary stream is divided arbitrarily into words of 6 bits and each combination (there are 64) coded into a 4 element ternary word. If all 81 combinations of ternary elements are considered there are found to be: a) 18 balanced words.

b) 14 pairs of words.

Two methods of pairing are: i) pairing positive with negative disparity words.

ii) pairing words with + and 0 pulses only with those with - and 0.

c) 32 unbalanced words which are transmitted without any attempt to balance them.

d) Three words ++++ 0000 and -- -- without transitions which are not used as the total of a5, b) and c) of 64 is sufficient.

Two 4 bit shift registers SR+ and SR- are required with gating to monitor errors which turn words into the non-used words ++++, 0000 and ----. These particular words may all be forbidden in one word position or used in two or three consecutive word positions as in the 3B2T case. A block schematic is given in Fig. 3.

Other codes have been considered for digital line systems and those which might use the above proposal are: 4B3T (and the MS43 variant).

3B2 Quaternary with shift registers monitoring the most positive and most negative excursions: indeed any such code could be used as long as there are more line transmission code combinations than binary coding combinations.

WHAT WE CLAIM IS: 1. A digital line transmission system employing a line transmission code involving three or more level coded combinations for transmitting binary coded information there being more line transmission code combinations than binary code combinations, the transmission system including means for detecting and indicating errors by indicating the reception of line transmission code combinations which are not used for binary code combinations in which the binary code bytes are mapped onto two sets of ternary bytes and the sets of ternary bytes are used alternately and the un-used code combinations differ for each set and the transmission system includes a receiver including two N stage shift registers, where N equals the number of bits in a ternary byte, and the first of the shift registers is arranged to receive positive line pulses whereas the second of the shift registers is arranged to receive negative line pulses and the outputs of the shift registers are applied to an AND gating field which detects the code combinations which are not used for binary code combinations.

2. A digital line transmission system as claimed in claim I in which timing pulses are derived from the received bit stream and are used to drive a divide by N circuit which controls the AND gates of the AND gating field.

3. A digital line transmission system as claimed in claim 2 in which the detection of an un-used combination is arranged to suppress one timing pulse.

4. A digital line transmission system as claimed in claim 3 in which an error output signal is used to activate a monostable device which controls the input to the divide by N circuit.

5. A digital line transmission system substantially as described with reference to the drawings accompanying the provisional specification.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

The result of the above process is that a single error originates a succession of monitoring point slips until the original phasing is restored. Pulse stretcher PS is arranged to give an output pulse with its longer than the succession of slips in nearly all cases and therefore a single error output for each input error providing the intervals between errors are long enough. This condition will normally be fulfilled in line transmission systems when one error per 106 elements is the error rate of interest. The symbol slipping arrangement is necessary to ensure that the error monitor synchronises itself at system startup.

Another code proposed for digital line system is the 6B4T code. (Note: There are not enough ternary words available to limit the disparity completely in this code). In this the incoming binary stream is divided arbitrarily into words of 6 bits and each combination (there are 64) coded into a 4 element ternary word. If all 81 combinations of ternary elements are considered there are found to be: a) 18 balanced words.

b) 14 pairs of words.

Two methods of pairing are:

i) pairing positive with negative disparity words.

ii) pairing words with + and 0 pulses only with those with - and 0.

c) 32 unbalanced words which are transmitted without any attempt to balance them.

d) Three words ++++ 0000 and -- -- without transitions which are not used as the total of a5, b) and c) of 64 is sufficient.

Two 4 bit shift registers SR+ and SR- are required with gating to monitor errors which turn words into the non-used words ++++, 0000 and ----. These particular words may all be forbidden in one word position or used in two or three consecutive word positions as in the 3B2T case. A block schematic is given in Fig. 3.

Other codes have been considered for digital line systems and those which might use the above proposal are: 4B3T (and the MS43 variant).

3B2 Quaternary with shift registers monitoring the most positive and most negative excursions: indeed any such code could be used as long as there are more line transmission code combinations than binary coding combinations.

WHAT WE CLAIM IS: 1. A digital line transmission system employing a line transmission code involving three or more level coded combinations for transmitting binary coded information there being more line transmission code combinations than binary code combinations, the transmission system including means for detecting and indicating errors by indicating the reception of line transmission code combinations which are not used for binary code combinations in which the binary code bytes are mapped onto two sets of ternary bytes and the sets of ternary bytes are used alternately and the un-used code combinations differ for each set and the transmission system includes a receiver including two N stage shift registers, where N equals the number of bits in a ternary byte, and the first of the shift registers is arranged to receive positive line pulses whereas the second of the shift registers is arranged to receive negative line pulses and the outputs of the shift registers are applied to an AND gating field which detects the code combinations which are not used for binary code combinations.
2. A digital line transmission system as claimed in claim I in which timing pulses are derived from the received bit stream and are used to drive a divide by N circuit which controls the AND gates of the AND gating field.
3. A digital line transmission system as claimed in claim 2 in which the detection of an un-used combination is arranged to suppress one timing pulse.
4. A digital line transmission system as claimed in claim 3 in which an error output signal is used to activate a monostable device which controls the input to the divide by N circuit.
5. A digital line transmission system substantially as described with reference to the drawings accompanying the provisional specification.