SU1388884A1 - Device for determining skill of a human operator - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to simulate the activity of a human operator of man-machine systems. The aim of the invention is to increase the accuracy of the calculations. The said goal is achieved by the addition of a block of delay elements and a second subtraction block to the device. The essence of the invention is that according to the data obtained during the experiment or practical activity of the operator, the limit value of the training level is calculated. The resulting ratio of the values of the limit and the real level of the operator's training can later be used to simulate the functioning of the equipment sample. 1 il. with

Description

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one

The invention relates to an advanced technique, in particular, to devices for simulating the activity of a human being - an operator of human-machine systems.

The purpose of the invention is to improve the accuracy of calculations.

The drawing shows a diagram of the proposed device.

The device contains a generator of 1 clock pulses, the first 2, second 3 and third 4 pulse counters, block

5 elements. delays, first block

6, tee, first multiplication unit 7, first adder 8, second multiplication unit 9, squaring unit 10, second subtracting unit 11 first subtracting unit 12, first unit

13 divisions, the second adder 14, the second division unit 15, the second memory unit 16, the display unit 17.

To determine the level of operator training, the marginal values of preparation for the type of activity under consideration are calculated by the formula

n-i

about - -1- 5 9i - ..: 9J ± iJ-9J

 n-2 f-g 2Q; ,, - (Qi-t-QuJ

where n is the number of experimental measurements;

Q - experimental values

measurements

The device works as follows.

Before starting work in block 16

memory value is entered

memory block 6 - the value of Q. (: -, ti). The state of the adder 14 is set to zero. The state of counter 2 is set to zero. The state of counter 3 is set to one. The state of counter 4 is set to two. The register of the multiplier of block 7 multiplies the value of two.

The Start signal, which is fed to the input of the pulse generator 1, sends a signal from it to the inputs of counters 2-4. At the same time, the contents of the first counter of counter 2 is set to one unit, the contents of counter 3 are equal to two, and the contents of counter 4 are equal to three.

According to the signal from counter 2, the contents of the first cell of the memory block 6 are fed to the input of the adder 8 and the input of the multiplication unit 9. The signal of the second counter 3, the contents of the second chey0

0 blocks

five

five

0

five

0 5

0

five

The ki of the memory block 6 is fed to the input of the multiplication unit 7 and the input of the unit 10. squaring. The signal from counter 4, through block 5 of the delay elements, the contents of the third cell of memory block 6 is fed to the input of the adder 8 and the input of the multiplier 9. In this case, in multiplication unit 7, the contents of the second cell of memory unit 6 are multiplied by two.

At the adder 8, the contents of the first and third cells of the memory block 6 are added together. In multiplication unit 9, the contents of the first and third cells of memory unit 6 are multiplied. In block 10, squaring is performed by squaring the contents of the second cell.

6 memories. In subtraction unit 12, the contents of adder 8 are subtracted from the contents of multiplication unit 7. In subtraction unit 11, the contents of multiplication unit 9 are subtracted from the contents of squaring unit 10. In dividing unit 13, the contents of subtracting unit 11 are divided by the contents of subtracting unit 12. On the adder 14, the result of the division block 13 and the contents of the adder 14 are added.

Then the oscillator 1 clock pulses the second pulse and the device continues to work according to the described algorithm. Generator I stops working when the last cell of memory block 6 is read. In this case, the signal from counter 4 stops the operation of generator 1. In this case, in block 15, the contents of adder I4 are divided by the contents of memory block 16. On display unit 17, the value of the marginal level of operator training, calculated by the formula, is highlighted.

Claims (1)

Invention Formula A device for determining the training of a human operator comprising a clock pulse generator, three pulse counters, two multiplicators, a first subtraction unit, two adders, two memory blocks, a squaring block and two division blocks, a clock pulse trigger input the device start input and the clock generator output pulses connected to the counting inputs of the first, second and third pulse counters, the bit outputs of the first and second pulse counters are connected respectively to the first and second address inputs of the first memory block, the information input of which is the information input of the device, the output of the first totalizer is connected to The first input of the first subtraction unit, characterized in that, in order to improve the computational accuracy, it contains a block of delay elements and a second subtraction unit, the bit outputs of the third The pulse generator is connected via a block of delay elements, respectively, to a third address input of the first memory block, the first output of which is connected to the input of the first multiplication unit and the input of the squaring block, the output of which is connected to the first input of the second subtraction unit, the second input of which is connected to the output of the second the multiplication unit, the first input of which is connected to the second output of the first memory block and the first input of the first adder, the second input of which and the second input of the second multiplication unit are connected to the third in the output of the first memory block, the output of the first multiplication unit is connected to the second input of the first subtraction unit, the output of which is connected to the first input of the first division unit, the second input of which is connected to the output of the second subtraction unit, and the output of the first division unit is connected to the input of the second adder, output which is connected to the first information input of the second dividing unit, the division resolution input of which is connected to the overflow output of the third pulse counter and the stop input of the clock generator, information The second input of the memory block is the setup input of the device, and the output of the second memory block is connected to the second information input of the second division block, the output of which is the output of the device. -