SU1387183A1 - Device for delaying pulsed signals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in pulsed digital radio devices to create a linearly varying delay of a reference pulse signal at a speed specified by a digital code. The invention allows to simplify this device in comparison with the prototype and increase its noise immunity. The device contains a register 1, the element AND-NOT 2, the element OR 3, the trigger 4, the counters 5 and 9 pulses, the generator 6 pulses, the trigger 7, the element 8, the bus 10 to set the initial voltage, the bus 11 delay code, the bus 12 control bus 13 output pulses bus 14 single signal and output bus 15. The device can operate in a mode with a linear increase in the delay time and in the mode with a constant value of the delay time. 1 il.

Description

(L

IS

with

00

00

with

The invention relates to a pulse technique and can be used in pulsed digital and radio devices to create a linearly varying delay of a reference pulse signal at a speed specified by a digital code.

The purpose of the invention is to simplify the device and increase its noise immunity.

The drawing shows the functional electrical circuit of the proposed device for the delay of pulse signals.

The device contains a register 1, the element AND-NOT 2, the element OR 3, the trigger 4, the second counter 5 pulses, the information inputs of which are connected to the outputs of the register 1, the generator 6 pulses, the trigger 7, the element And 8, the first input of which is connected to the output of the generator 6 pulses, and the second with a single output of the trigger 7, the first counter of 9 pulses, to the information inputs of which are connected the information outputs of the counter 5, the transfer output of which is connected to the second input of the element OR 3, the output of which is connected to the C input of the trigger 4, S-input which is soy dinen with the output of the element AND-NOT 2, the third input of which is connected to the zero output of the trigger 7 and the recording information input of the counter 9, the subtractive input of which is connected to the output of the element And 8 and the summing input of the counter 5, to the information recording input of which the zero output of the trigger is connected 4, the D-input of which is connected to the zero thickness of the power source, the initial position setting bar 10, which is connected to the R input of the trigger 4 and to the reset input of the counter 9, delay code 11, which are connected to the information inputs of the register 1, control bar 12 phenomenon, which is connected to the first input element AND-NOT 2, the bus 13 input pulses, which is connected to the second input element AND-NOT 2 and with the S input of the trigger 7, the signal 14, which is connected to the D input of the trigger 7, output bus 15, which is connected to the output of the borrowing of the counter 9, with the R input of the trigger 7 and with the first input of the OR 3 element.

Trigger 4 at the C input is set to zero position by the O-1 signal drop at this input, since a zero is permanently connected to its D input, trigger 7 at the C input is set to 1 at the O-1 signal drop. This input, since a source 14 of a single signal is permanently connected to its D-input. The trigger 4 at the S-input is set to one position when a zero level pulse arrives at this input, the trigger 4 at the R input is set to zero position when a single level pulse arrives at this input. Trigger 7 on the R input is set to zero

the position when a zero level pulse arrives at this input.

When a pulse arrives at the summing input of the counter 5, a unit is added to its contents on the leading edge (perepad O-1) of the incoming pulse, when a pulse arrives on the subtracting input of the counter 9, its unit is taken off on the leading edge (differential O-1) of the incoming momentum. When a single pulse arrives at the information recording inputs - the WR inputs of counters 5 and 9 - the information code is stored in them, which is located on the information D-BXO of the corresponding counter. In the event that the record of the information of the counter 5 has a single signal level at the input, the counter 5 at the summing input and the counter 9 at the subtractive input do not work, i.e. The inputs for recording meter information have priority over the summing and subtracting inputs. When a single pulse arrives at the reset input of the counter 9, the latter is set to the zero position regardless of which signals act on its other inputs, i.e. reset input takes precedence over other counter inputs. At the output of the transfer — the CR output of counter 5 — a zero signal appears if the counter is full, i.e., if the number 1 is written in it, where n is the counter size 5, there is no unit pulse at the summing input of the counter . The output of the loan — the BR output of counter 9 — appears a zero signal if the counter is in the zero position and

subtractive input is missing a single pulse. The information outputs of counter 5 are the outputs of counter bits 5. The bit width of counters 5 and 9 is the same.

40

45

Element1 OR 3 performs a logical OR function for zero-level signals, i.e. Normally, at the inputs of the element OR 3, there should be single signals, then there is a significant signal at its output, when a zero signal at the output of the element OR 3 appears at one or both of the inputs, a zero signal also appears.

The duration of the pulse ti of the generator 6 is chosen not less than the value sufficient for the accurate operation of the counter 5 on the totalizing input and the counter 9 on the subtracting input. The duration of the pause of the generator pulses 6 must be no less than the value of t а U + tS + tc5, where t ta is the response time of the counter 9 for the loan output, i.e. the time from the end of the pulse at the subtracting input to the moment when the zero signal appears at the output of the loan with the zero content of counter 9; the trigger time of 7 on the R input, i.e. the installation time of the trigger 7 to the zero position; the response time of the counter 9 at the information recording input, i.e. time from the moment when the signal appears at the input of the information recording and until the moment of installation is recorded C9

There are two modes of operation of the device - the main mode of operation with a linearly increasing delay value of the input pulse, in this case a single signal is sent to the control bus 12, and an additional operating mode with a constant delay value, in this case a zero signal is given to the control bus 12 .

Pulse delay device

Beth code in the counter 9 and B-0 signals works as follows.

loan unit + 01

laziness at the exit

signal;

element response time

OR 3 by O-1 differential, i.e. time

In the initial state in register 1 a code of the number N is written, which determines the magnitude of the delay of the first input pulse and the ratio of which increases from the time of the appearance of the unit 15 and the delay of the subsequent input pulses, the signal at the input of the element OR 3, triggers 4 and 7 are in zero position - and before the occurrence of unitization, counters 5 and 9 recorded the code of the numerical signal at the output of the element N. Therefore, the transfer output of the counter is OR 3 (provided that there is a single signal on the other 5, a single signal exists) ; OTU OR 3 pervrem actuation of trigger 20 April Nome input and the output of the counter 9 Loan

there is a single signal permitting the operation of the trigger 7 at the C input. The device is reset to its initial state after writing the N number code from the bus into register 1.

on the C input, i.e. the installation time of the trigger 4 to the zero position when the difference signal O-1 at the C-input;

 - the response time of the counter 5 Tc 11 by impulse delivery to the bus 10, while

at the input of the information recording, i.e. the time from the moment when the signal at the input of the recording of information of the counter 5 appears to the moment of setting the recorded code in the counter 5.

trigger 4 is set to the zero position, a single signal appears at its zero output, which writes the contents of register 1 to the counter 5 — the code of the number N; moreover, the period T of the he-Zo pulses is zero;

nerator 6 should be

 I t

I t: + t2 ti + tc9 + 1 „+ C + t (.j + LM + W) The initial setting impulse duration, supplied by 10, must be no less than the period of the generator impulses.

A zero level pulse is output to the output bar 15, the duration of which is tn t. If it is necessary to increase the loan of which a zero signal appears, arriving through the OR element 3 at the C input of the trigger 4, and also the trigger 7 setting zero, at the zero output of which a single bus appears 35 a signal permitting the operation of the element AND NOT 2 at the first and second inputs and entering the record information of the counter 9. At the time of the end of the pulse on bus 10, the contents of the counter 5 is the code of the number N — recorded in counter 9, at the output of the loan which ends a zero signal (i.e. single signal), p differential O-1 which confirmed the zero position of the trigger 4 - the device is reset state.

40

the duration of the delayed pulse to the output bus 15 is connected to the one-oscillator, the issuing pulse of the desired duration, if necessary to have a single-level pulse on the output bus, the inverter is connected to it.

Bus 11 is supplied with a minimum delay value code — a code of the number N, while the minimum delay value of the input pulse is processed by the device,. If for recording the code in which the zero signal appears, the signal arrives through the OR element 3 at the C input of the trigger 4, and also sets the trigger 7 to the zero position, at the zero output of which appears a single bus 35 signal enabling the operation of the element AND - NOT 2 at the first and second inputs and entering the record information of counter 9. At the time of the end of the pulse on bus 10, the contents of counter 5 - the code of the number N - is recorded in counter 9, at the output of the loan which ends a zero signal (i.e. is a single signal) The DEPO-1 of which confirms the zero position of the trigger 4 - the device is set to its initial state.

In the case when a single signal is applied to the control bus 12, i.e. set operation mode with linearly varying be40

45

the delay of the input pulses when the first input arrives on the bus 13

Since the recorder needs a recording signal, then one of the busses 50 of the pulse triggers element I-NE 2 and 11 is allocated for this signal, and the sub-zero signal from its output is set to the information recording input, the trigger 4 is set to one.

a zero output of which a zero signal appears, enabling the operation of counter 5 on the summing input. At the same time

gistra 1.

The input pulse must be fed to the input bus 13 no earlier than after

the output of the delayed previous pulse is 55 from the bus 13 arrives at the C-input of the pulse, otherwise the input pulse of the trigger 7 and along its leading edge

(differential O-1) sets it in a single position. At zero trigger output

perceived as an interference and the device does not respond to it.

There are two modes of operation of the device - the main mode of operation with a linearly increasing delay value of the input pulse, in this case a single signal is sent to the control bus 12, and an additional operating mode with a constant delay value, in this case a zero signal is given to the control bus 12 .

Pulse delay device

The signals works as follows.

the loan of which a zero signal appears, arriving through the element OR 3 at the C input of the trigger 4, and also setting the trigger 7 at the zero position, at the zero output of which appears a single 35 signal permitting the operation of the element AND NOT 2 at the first and the second inputs and the input of the information record of the counter 9. At the time of the end of the pulse on bus 10, the contents of the counter 5 — the code of the number N — are recorded in the counter 9, at the output of the loan of which a zero signal ends (i.e. a single signal appears) on the O-1 differential which is confirmed are zero position trigger 4 - the device is reset state.

In the case when a single signal is applied to the control bus 12, i.e. set operation mode with linearly varying be40

45

7, a zero signal appears, closing the NAND 2 element and enabling the operation of the counter 9 on the subtracting input. A single signal appears at the single output of trigger 7, allowing the generator 6 to pass pulses through the AND 8 element to the summing input of counter 5 and to the subtracting input of counter 9. Each pulse from the output of the AND 8 element on its leading edge subtracts one from the contents

sets the trigger 7 to zero position, opens the IS-NOT 2 element at the third input, counters 9 records the contents of counter 5 — the code of the number 3 N, ends the zero signal at the output of the counter 9 loans (i.e., a single signal appears) and on its O-1 differential, trigger 4 is set to the zero position. A single signal from the zero output of the trigger 4 enters into the counter 5 the contents of the register

counter 9 and adds one to the content of the 10 1 - the code of the number N. the counter 9 and on the output bus 15 a zero signal appears, coming through the OR element 3 to the C input of the trigger 4 and setting the trigger 7 to the zero position, at the zero output of which a single signal appears, the opening element AND-NOT 2 on the third entrance and incoming information recording

. 15

And 8, from the moment the second input pulse arrives on the bus 13, the output bus 15 is given a pulse of zero level of duration tn, delayed relative to the second input pulse for a time (accurate to the value of T), the code 9 is written to the counter 9, and the counter 5 - the code number N.

Upon admission to the groove 13 of the third and

counter 9, which records the contents of the next 20 pulses, the device operates

the counter of the counter 5, equal to N + N 2N, while at the output of the counter 9 and on the output bus 15 ends a zero signal, on the difference O-1 of which the trigger 4 is set to the zero position.

At the zero output of flip-flop 4, the magnitude of the delay 25 of the next input single signal arrives at the pulse input — the number (i + l) N recorded for recording the information of counter 5, while the counter 5 is disabled on the summing input and is written to it

as described above, issuing an i-ro pulse to the output bus 15 on the output bus 15, a zero-level pulse delayed relative to the input pulse for the time t i NT, and generating a code

the contents of register 1 is the code of N. Counter 9i

When, in the process of generating the delay code of the next input pulse, the counter 5 should generate a number, especially in pause after the Nth pulse, its upstream capacity, i.e. the number is greater

from the output of the element AND 8 to the output busbar 15 a zero-level pulse is output with duration in, delayed relative to the first input pulse for a time (up to the value of T), counter 9 records the code of the number 2N - the code indicating that the delay of the second input pulse is equal to t 2NT, and code 5 is recorded in counter 5.

35

than (), then at the moment of the end of the pulse recording in the counter 5 the number (), at its transfer output a zero signal appears through the element OR 3 at the C input of the trigger 4. When the next pulse appears at the summing input of the counter 5 at its transfer output, a zero signal ends (i.e. a single signal appears) and the trigger 4 is set to the zero position. A single signal from the zero output of the trigger 4 writes into the counter 5 the contents of the register 1 - the number N, and prohibits the operation of the counter 5 on the summing input. Then, when a zero signal appears at the output of the counter 9 loan and the trigger 7 is set to the zero position, the AND-HE element 2 is opened at the third input and the counter 9 is recorded in the same way as described, the contents of the counter 5 equal to the code of the number N. Thus, in the case the overflow of the counter 5 in the device is set

40

When a second input pulse arrives on bus 13, similarly to the previous case, the NE-HE element 2 is triggered, trigger 4 is set to one position, allowing counter 5 to work on the summing input, trigger 7 is set to one position, closing AND-HE 2, allowing the counter 9 to work at the subtracting input and permitting the pulse of the generator 6 to pass through the AND 8 element. Each pulse from the output of the AND 8 element along its leading edge deducts

than (), then at the moment of the end of the pulse recording in the counter 5 the number (), at its transfer output a zero signal appears through the element OR 3 at the C input of the trigger 4. When the next pulse appears at the summing input of the counter 5 at its transfer output, a zero signal ends (i.e. a single signal appears) and the trigger 4 is set to the zero position. A single signal from the zero output of the trigger 4 writes into the counter 5 the contents of the register 1 - the number N, and prohibits the operation of the counter 5 on the summing input. Then, when a zero signal appears at the output of the counter 9 loan and the trigger 7 is set to the zero position, the AND-HE element 2 is opened at the third input and the counter 9 is recorded in the same way as described, the contents of the counter 5 equal to the code of the number N. Thus, in the case the overflow of the counter 5 in the device is set

one of the contents of counter 9 and the minimum set delay delays the unit to the contents of counter 5. However, since before opening element 8 of counter 8, the content of counter 9 is 2N, only after the {2N) -ro pulse appears a zero signal at the output of the loan counter 9 and on the output bus 15. The contents of counter 5 at this moment is N-4-2N 3N. Zero signal from the output of the loan counter 9

55

ki (the delay of the first input pulse) and then the cycle of operation is repeated, i.e. the delay of subsequent pulses increases linearly.

In the event that the number () is a multiple of the number N, after the end of the () th pulse, zero sigals appear at the input of the counter 9, and the output sets the trigger 7 to the zero position, the AND-NOT 2 element opens at the third input , counter 9 records the contents of counter 5 — the code of the number 3 N, a zero signal ends at the output of the loan of counter 9 (i.e., a single signal appears) and by its O-1 difference, the trigger 4 is set to the zero position. A single signal from the zero output of the trigger 4 enters into the counter 5 the contents of the register

 1 is the code of the number N. Thus, in pause after the (2N) -ro pulse from the output of the element

10 1 - the code of the number N. Thus, in pause after the (2N) -ro pulse from the output of the element 15

And 8, from the moment the second input pulse arrives on the bus 13, the output bus 15 is given a pulse of zero level of duration tn, delayed relative to the second input pulse for a time (accurate to the value of T), the code 9 is written to the counter 9, and the counter 5 - the code number N.

Upon admission to the groove 13 of the third and

 delay values of the next input pulse - the number (i + l) N, recorded by

as described above, issuing an i-ro pulse to the output bus 15 on the output bus 15, a zero-level pulse delayed relative to the input pulse for the time t i NT, and generating a code

delay values of the next input pulse - the number (i + l) N, recorded by

counter 9i

When, in the process of generating the delay code of the next input pulse, the counter 5 should generate a number that exceeds its capacity, i.e. the number is greater

its upward capacity, i.e. the number is greater

than (), then at the moment of the end of the pulse recording in the counter 5 the number (), at its transfer output a zero signal appears through the element OR 3 at the C input of the trigger 4. When the next pulse appears at the summing input of the counter 5 at its transfer output, a zero signal ends (i.e. a single signal appears) and the trigger 4 is set to the zero position. A single signal from the zero output of the trigger 4 writes into the counter 5 the contents of the register 1 - the number N, and prohibits the operation of the counter 5 on the summing input. Then, when a zero signal appears at the output of the counter 9 loan and the trigger 7 is set to the zero position, the AND-HE element 2 is opened at the third input and the counter 9 is recorded in the same way as described, the contents of the counter 5 equal to the code of the number N. Thus, in the case the overflow of the counter 5 in the device is set

minimum set delay value minimum set delay

ki (the delay of the first input pulse) and then the cycle of operation is repeated, i.e. the delay of subsequent pulses increases linearly.

In the event that the number () is a multiple of the number N, zero signals appear at the end of the () -th pulse at the input of the counter 9, and at the transfer output of the counter 5, and, accordingly, the zero signal appears at the output of the element OR 3. The zero signal from the output of the credit of the counter 9 sets the trigger 7 to the zero position, the AND-NOT 2 element opens on the third input and the number code () is written to the counter 9, but the trigger 4 is not set to the zero position at the moment of the end of the zero signal at the output of the loan counter 9.

When the next input pulse arrives on the bus 13, the AND-NOT 2 element is triggered and the zero signal from its output confirms the single position of the trigger 4, moreover, on the leading edge of this

A device for delaying pulse signals containing a register, an AND-NIE element, an OR element, a pulse-impulse generator is set to a single position trigger 7, resulting in 5 ow, the first trigger, AND element, to the inputs is closed at the third input of which the output of the generator AND-NOT 2 and the generator pulses 6 start the pulses and the single output of the first trigger to pass through the element AND 8 - goes from, the first pulse counter, subtracting the input pulse delay, the equal input of which is connected to the output hydrochloric left-t (). The first impulse from the output of the 20 And, the setting bar of the initial state of the element And 8, arriving at the summing input of counter 5, sets it to the zero position. The output of the transfer of counter 5 terminates a zero signal (i.e., a single signal appears) and a trigger 4, which is connected to the reset input of the first pulse counter, the delay code bus, which are connected to the information inputs of the register, the control bus that is connected to the first entry

The O-1 signal of this signal is set to 25 NAND elements, the input busbar, which

is in zero position. A single signal from the zero output of the trigger 4 is input to the information record of the counter 5, inserts the code number N. The trigger 4 is in the zero position before the end is disconnected from the second input of the NAND element, the output bus, which is connected to the output of the loan of the first pulse counter and with the first input of an OR element, characterized in that, in order to simplify the device processing of the delay and arrival on the bus and increase its noise immunity.

13 of the next input pulse, after which a new delay cycle of input signals begins, the delay of the first pulse in which is NT, and the delay of each subsequent pulse increases by NT.

When a pulse arrives on bus 13 - interference before a delayed pulse is issued on the output bus 15, the device fails to work

A second trigger, a second pulse counter are entered into it, the D input of the first trigger is connected to the single signal bus, and its C input is connected to the second input of the NAND element, the third input of which is connected to the zero output of the first trigger pulse counter, the subtracting input of which is connected to the summing input of the second pulse counter, the output of the second pulse is entered, the second trigger, the second pulse counter, the D input of the first trigger is connected to the single signal bus, and its C input is connected the second input of the NAND element, the third input of which is connected to the zero output of the first trigger and to the information entry input of the first pulse counter, the subtractive input of which is connected to the summing input of the second pulse counter, doesn’t

In addition to this, the unit polo-40 of which is connected to the second input is only confirmed by the tracking of the trigger 7 (which is already the OR ment, the output of which is connected

in a single position), and the element AND-HEC C-input of the second trigger, zero output

2 does not work, since it is closed which is connected to the recording input for the reason that there is no single signal on the second pulse counter, the information output of the trigger 7. Its output outputs are connected to

To change the delay value, the non-information inputs of the first counter

It is necessary to write into register 1 the code of the new sign-impulses, the reset input of which is connected

delay the number of NI and apply a pulse to the bus 10. After that, the device delays the input pulses for a time, linearly increasing relative to NiT.

If it is necessary that the delay of the input pulse is constant, a zero signal must be sent to the bar 12 and then, since the trigger 4 is in the zero position 50

with the R-input of the second trigger, to the S-input of which the output of the NAND element is connected, the outputs of the register are connected to the information inputs of the second pulse counter, the D-input of the second trigger is connected to the zero power supply source, the output of the loan is connected to the R-input of the first trigger first pulse counter.

After the device is reset, a single signal from its zero output will be permanently located at the input of the record of information of the counter 5, in which the code of the number N is written, and the operation of the counter 5 on the summing input is prohibited, i.e. linear accumulation of the delay is not performed, it is equal to NT for each input pulse a.

Claims (1)

Invention Formula A device for delaying pulse signals containing a register, an AND-NIE element, an OR element, a pulse generator, a first trigger, an AND element, to the inputs of which a pulse generator output is connected and a single output of the first trigger, the first pulse counter, subtracting the input of which is connected to the output of the element I, the setpoint bar of the initial state, the first trigger, the element I, the inputs of which are connected to the output of the pulse generator and the single output of the first trigger, the first pulse counter, the subtracting input of which is connected to out one element And, the initial state setting bus, which is connected to the reset input of the first pulse counter, the delay code bus, which are connected to the information inputs of the register, the control bus, which is connected to the first input element and NOT, input bushes, which element and NOT, input bushes, which connected to the second input of the NAND element, an output bus that is connected to the output of the loan of the first pulse counter and to the first input of the OR element, characterized in that, in order to simplify the device and increase its noise immunity. five A second trigger, a second pulse counter are entered into it, the D input of the first trigger is connected to the single signal bus, and its C input is connected to the second input of the NAND element, the third input of which is connected to the zero output of the first trigger pulse counter, the subtracting input of which is connected to the summing input of the second pulse counter, output peredo50 with the R-input of the second trigger, to the S-input of which the output of the NAND element is connected, the outputs of the register are connected to the information inputs of the second pulse counter, the D-input of the second trigger is connected to the zero power supply source, the output of the loan is connected to the R-input of the first trigger first pulse counter.