SU1386987A1 - Homogeneous computation medium cell - Google Patents

Abstract

A homogeneous computing environment cell is related to computing technology and can be used to build homogeneous computing environments, for example. matrix and systolic processors. The purpose of the invention is to expand the functionality by setting an arbitrary delay of information transfer. The cell contains command registers, RS-triggers, D-trigger, arithmetic logic element, programmable delay blocks, two multiplexer groups, decoder, switch, OR elements, OR element, AND elements, NOT element, delay elements. The essence of the invention is the ability to set an arbitrary amount of delay for each of the information outputs of the processor cell and the implementation of an arbitrary function of switching information inputs and outputs of the cell when combining operational and transit functions. 1 hp f-ly, 4 ill. with p

Description

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The invention relates to computing and can be used in the construction of homogeneous computing environments (EIA), for example, systolic processors.

The purpose of the invention is to expand the functionality by setting an arbitrary delay of information transfer.

FIG. 1 shows a functional diagram of a homogeneous computing environment; in fig. 2 - functional diagram of the block programmable delay; in fig. 3 - fragments Е1т of the computing environment based on the proposed cell; in fig. 4 - timing diagram of the main elements of the cell when performing the operation “Logical addition.

Cell-OBC (Fig. 1) contains registers 1 and 2 of the program with fields (1.1 -1.4 - fields of delay codes, respectively, for the information outputs of the cell; field 1.5-1.7; input addresses of the first and second operands and transit, respectively; field 2. - 2.4 - output addresses, respectively, for informational inputs of the cell; field 2.5 — field of the opcode for which the cell is configured), RS-flip-flop group 3.1-3.3, D-flip-flop 4, arithmetic logic unit 5, group of 6.1-6.4 programmable delay ( BPZ) group of multiplexers 7.1-7.3, group of multiplexers 8.1-8.4, decoder 9 to yes operations, switch 10, elements OR 1-14 elements OR-NOT 15, elements AND 16-20, element 21, first 22 and second 23 delay elements, program control input input 24, program input 25, information inputs 26.1-26.4, clock input 27, reset input 28, output 29 of the program output and information outputs 30.1.-30.4.

Block 6.1 -6.4 programmable delay (BPZ) group (Fig. 2) contains a counter 31, RS-flip-flop 32, the elements OR 33 and 34, the element OR-NOT 35, the elements AND 36-38 and the element 39 of the delay.

Registers 1 and 2 of the program are used to store control information.

The first 3.1 and second 3.2 RS-flip-flops are designed for intermediate storage of the first and second operands respectively, the third RS-flip-flop 3.3 is for intermediate storage of the third operand (transit), and the D-flip-flop 4 is for storing the transfer and taking into account its next addition when two single-digit numbers in the ALE 5. The ALE 5 serves to perform operations on the first and second operands stored in accordance with triggers 3.1 and 3.2. BPZ 6.1-6.4 is designed to form an information release synchronization signal, respectively, for output multiplexers 8.1-8.4.

The group of multiplexers 7.-7.3 serves to transfer data to the triggers 3.1-3.3, respectively, from the information inputs 26.1-26.4, depending on the address information stored in fields 1.5-1.7.7 of the register 1. The group of multiplexers 8.1-8.4 is intended to issue data to informational outputs 30.1-30.4, respectively, depending on the address information stored in field 2.1-2.4 of register 2. The decryptor 9 of the operation code is designed to generate control signals that organize the operation of the cell. Switch 10 serves to loop the constant in register 1 in the mode

5 “Constant generation.

The IDN Element 11 is designed to assemble signals that allow pulses to pass through the I register, OR 12 to assemble signals arriving at the first information inputs of output multiplexers 8.1–8.4, OR 13 element to assemble the BPS 6.1–6.4 initiation signals, OR 14 - for assembling the zeroing signals of triggers 3.1 - 3.3, element OR-NOT 15 - for generating a single signal after the last information output from the cell on information outputs 30.1-30.4, elements 16 and 17 - for generating synchronization signals according to GOVERNMENTAL for registers 1 and 2.

The elements AND 18 and 19, the element OR 12 and the relations arising from them are intended for organizing the mutual exclusion of the operational mode and the constant generation mode. Element And 19, in addition, serves to block a single signal of the result of the ALE 5 in the case of an IS-NOT operation (logical multiplication with inversion) when the triggers are zeroed. 3.1-3.3. Element AND 20 serves to enable the passage of pulses from input 27 after the last information output from the cell at outputs 30.1-30.4. Element NOT 21 is designed to block the operation of the decryptor 9 when programming a cell.

The first delay element 22 serves to delay the synchronization signal of the recording of the transfer bit from the ALE 5 to the trigger 4 for the duration of the transients to output information on outputs 30.1-30.4. The second delay element 23 is designed to delay the zeroing of the triggers 3.1-3.3 for the duration of the transients.

0 write transfer to trigger 4.

The BFZ counter 31 (Fig. 2) serves as the reference for the time interval of the programmable delay, depending on the values of the programmable delay codes stored in fields 1.1 -1.4 of register 1 of program 5.

The trigger 32 BPZ is designed to indicate the perfect release of information, respectively, on the outputs 30.1-30.4. The element OR 33, the element AND 36 and the relations arising from them serve to organize the work of the counter 31 with saturation in the state "O.

The OR-NE 35 element is used to form the setup signal for counter 31, AND 37 and 38 are for allowing clock pulses to pass through the BOD to the synchronous inputs of multiplexers 8.1-8.4, respectively, in the operating-transit mode and the constant generation mode, the element OR 34 - to assemble the signals that synchronize the operation of the corresponding multiplexers 8.1-84, delay element 39 for the single generation of the information output signal at the first BFB outputs in the operational-transit mode.

A single signal at the installation input of the counter 31 BPZ corresponds to the recording of information in this counter, and the zero level of the signal at its installation input enables the counting mode of the counter 31.

Cell OBC works as follows.

Before starting the task, the cell is programmed to perform certain functions. When programming the cell at input 24, a single signal level is established, which, firstly, arriving at the first inputs of the And 16 and 17 elements, opens them for the corresponding information output 30.1-30.4 cells, and. field 2.5 stores the operation code for which the cell is configured. Then, a single pulse is applied to the cell input 28, which zeroes the triggers

5 3.1-3.3 and 4 and counters 31 BPZ 6.1-6.4. After that, the work of the cell can proceed in the following modes: operational, transit and constant generation mode. Operational and transit modes can flow simultaneously. In constant generation mode, other cell operation modes are prohibited.

Operational transit mode. In this mode, the processing of incoming

, from certain informational inputs 26.1-26.4 operands in the ALE 5 and outputting the result of the operands and transit to certain information outputs 30.1-30.4 with the necessary delays, which are implemented using BPZ 6.1-6.4. The operation code stored in field 2.5 of register 2 is converted in decoder 9 into a unitary code, which is fed to the control input of the SLE 5, thereby specifying the type of operation it performs. In this mode, the discharge at the output of the decoder 9, corresponding to the operation “Constant generation, goes to the second direct and second inverse inputs of elements And 18 and 19, respectively, allowing the signal from the output of the SLE 5 to flow and prohibit

25

clock pulses from input 27 PE n constant supply from register 1 to the weekend

sync inputs of registers 1 and 2 of the program and, secondly, through the element NOT 21 it prohibits the operation of the decoder 9, on the outputs of which zero signals are indicated. From the output of the decoder 9, corresponding to the "Constant generation" mode, the zero signal arrives at the control input of the switch 10, which prohibits the cycling of the information output and the input of the register 1 and allows the passage of information from the input 25 of the cell to the multiplexers 8.1-8.4. This signal also arrives at the sixth inputs of the BPS 6.1-6.4, prohibiting the passage of clock pulses through the elements of AND 38 and OR 34 to the first outputs of the BPZ 6.1-6.4 and preparing for the opening of the jr for passing the clock pulses of the And 37. According to the input addresses of the first and the second operands and transit, stored respectively in the field x 1.5-1.7 of register 1, according to the clock pulses received through the input 27 of the cell to the synchronous inputs of the multiplexing input of the register I. Through the input 40 of the 7.1-7.3 sor, the input

25 cells in succession, discharge information is entered into the tuning information and advanced along the shift registers 1 and 2 to the output 29 of the cell, which makes it possible to sequentially connect the registers 1 and 2 of the cell programs in the OBC (Fig. 1 and 3).

The end of programming is done by setting the signal to zero at the input of 24 cells, which prohibits

45

information from certain inputs 26.1 - 26.4 to the corresponding triggers 3.1-3.3. The first and second operands are stored respectively in triggers 3.1 and 3.2, and the transit is in trigger 3.3. At the output of the ALE 5, the result of the operation on the contents of the triggers 3.1 and 3.2 is formed, and through the elements AND 19 it arrives at the first input of the element OR 13, the remaining inputs of which receive information from the direct outputs of the triggers

Reception and promotion of information on the register- 3.1-3.3. With the appearance of a single signal

T L1Uu LI fMlOriOlirQOT nQ P Agi I.I G U f n TI ,,. .. ". Pl..p.1.p .." .., ..

frames 1 and 2 and allows the operation of the decoder 9. Upon completion of programming, the FIELD registers 1 and 2 store the following information: field 1.1 -1.4 stores the delay codes, respectively, for information

one of the operands, transit, or the result of the ALE 5 at the output of the element OR 13, a single signal is generated, which, arriving at the third inputs of the BZB 6.1-6.4 trigger, initiates their operation to count a certain

inputs 30.1-30.4 cells; the field 1.5-1.7 stores the delay in the corresponding informant of the input addresses of the first and second operands and transit, respectively; Paul 2.1 - 2.4 Register 2 stores the output addresses of the socionial output 30.1-30.4. The initial zero state of counters 31 BPZ 6.1-6.4 leads to the appearance of a zero signal on

responsibly for informational exits 30.1-30.4 cells, and. field 2.5 stores the operation code for which the cell is configured. Then, a single pulse is applied to the cell input 28, which zeroes the triggers

5 3.1-3.3 and 4 and counters 31 BPZ 6.1-6.4. After that, the work of the cell can proceed in the following modes: operational, transit and constant generation mode. Operational and transit modes can flow simultaneously. In constant generation mode, other cell operation modes are prohibited.

Operational transit mode. In this mode, the processing of incoming

 from certain information inputs 26.1-26.4 operands in the ALE 5 and outputting the result of the operands and transit to certain information outputs 30.1-30.4 with the necessary delays, which are implemented using BPZ 6.1-6.4. The operation code stored in field 2.5 of register 2 is converted in decoder 9 into a unitary code, which is fed to the control input of the SLE 5, thereby specifying the type of operation it performs. In this mode, the discharge at the output of the decoder 9, corresponding to the operation “Constant generation, goes to the second direct and second inverse inputs of elements And 18 and 19, respectively, allowing the signal from the output of the SLE 5 to flow and prohibit

five

filing a constant from register 1 for the weekend

filing a constant from register 1 for the weekend

multiplexers 8.1-8.4. This signal also arrives at the sixth inputs of the BPS 6.1-6.4, prohibiting the passage of clock pulses through the elements of AND 38 and OR 34 to the first outputs of the BPZ 6.1-6.4 and preparing for the opening of the jr for passing the clock pulses of the And 37. According to the input addresses of the first and of the second operand and transit, stored respectively in the field x 1.5-1.7 of register 1, the clock input pulses are received through the input 27 of the cell to the synchronous inputs of the multiplex 40 7.1-7.3.

five

information from certain inputs 26.1 - 26.4 to the corresponding triggers 3.1-3.3. The first and second operands are stored respectively in triggers 3.1 and 3.2, and the transit is in trigger 3.3. At the output of the ALE 5, the result of the operation on the contents of the triggers 3.1 and 3.2 is formed, and through the elements AND 19 it arrives at the first input of the element OR 13, the remaining inputs of which receive information from the direct outputs of the triggers

3.1-3.3. With the appearance of a single signal

 f p TI ,,. .. ". Pl..p.1.p .." .., ..

one of the operands, transit, or the result of the ALE 5 at the output of the element OR 13, a single signal is generated, which, arriving at the third inputs of the BZB 6.1-6.4 trigger, initiates their operation to count a certain

delays on the corresponding information delay on the corresponding information output 30.1-30.4. The initial zero state of counters 31 BPZ 6.1-6.4 leads to the appearance of a zero signal on

i output of the element OR 33 and at the first inputs of the elements OR-NOT 35 and I 36, which organizes the operation of the counter 31 with saturation in the state "O and with a zero signal at the third input of the BPZ 6.1-6.4 allows recording information on the negative clock pulse into it arriving from the fifth BPZ input through an OR-NOT 35 element to the installation input of the counter 31, delays codes from fields 1.1 are recorded -

The outputs from vykhbdov 30.1-30.4 on the second outputs of all BPS 6.1-6.4 indicate zero signals, which lead to the appearance of a single signal at the output of the OR-NOT 15 element. This signal permits the passage of the next clock pulse through the element 22 of the trigger for the synchronous input of the trigger 4, in which the bit of transfer of the ALE 5 is recorded to take it into account at the next data processing step, and through register register elements 1. 4, the corresponding delay information Ju-22 and 23, and OR 14 - national outputs 30.1–30.4, into the trigger zero reset inputs 31 3.1-3.3 and three-bpz 6.1-6.4, respectively An inverted input of an element E 19, which when recording information into a counter 31, leads to an indication of a zero signal per output arriving at the installation input of the element OR 13. This signal, after this counter, is fed to the input of the stupon zeroing through the third inputs of the BPS 6.1-6.4 I trigger 32, the inverse output of which to the second inputs of the elements OR NOT 35 and I is indicated by a single signal, which, And 36, prohibits the counting mode of the input I counter through the delay element 39 at WTO-31 and enables next negative - I swarm direct input element And 37 podgotav th clock pulse recording information in Lebanon I to its opening for the passage of this counter. The next I-clock pulse from the fifth input to the trans-20 code of the delays from the fields 1.1 –1.4 and the BPZ next exit occurs. After writing the delayed-gist code 1 to the counters 31, respectively, the BPZ ki to the counter 31 at the output of the OR element OR 336.1-6.4 is similar to that considered. A single signal that is indicated by the differential output of operands is differentiated, it prohibits the recording of information in the 31zit counter or the result of the SLE 5 on information and prepares its operation in the counting outputs 30.1–30.4 of the cell is achieved. When a single signal 25 appears, the corresponding programming of the fields at the output of the OR 13 element is at setting-2.1-2.4 of register 2.

A zero signal is set at the input of counter 31, and element 36 is opened to pass clock pulses from the fifth BPZ input to the counting subtracting input of counter 31. The time delay begins counting, after which the counter 31 goes to the zero state, which through the OR elements 33 and 36 leads to the prohibition of the counting mode of the counter 31 BPZ groups 4.1-4.4, and post 30

Thus, in this mode, it is possible to issue with different delays to the information outputs of the cell of the first and second operands, transit and the result of the ALE, which is important in organizing programmable systematic structures in which the streams of input operands and intermediate results in the OVS have different and. changing directions. When programming a pop-up for the third inverse input of the element and 37, —leaf 2.1–2.4 of register 2 as issuing it for opening, for passing the clock output outputs 30.1–30.4 of PE only pulses from the fifth input to the first exit of the input operands and transit the trigger-BPZ group 6.1-6.4.rov 3.1-3.3 occurs the implementation of the operation of extended transit only,

By the next clock pulse, in-40 of which the input operands with different

first, the elements AND 37 and OR .34 delays for each information-BPZ synchronize the output of information through certain output multiplexers 8.1-8.4 to the corresponding information outputs 30.1-30.4 according to the corresponding output 30.1-30.4 passes through cells without processing on the SLE 5. Time diagrams for basic cell elements illustrating the operation but transit

corresponding output addresses that are stored — by the example of the operation “Logic in fields 2.1–2.4 of register 2, and, secondly, sets trigger 32 to one state, which, after issuing information from the cell, closes the AND element 37 for the passage of clock pulses until the next recording of information and the initiation of work of the corresponding BPZ 6.1–6.4. In general, various delay codes can be stored in fields 1.1–1.4 of register 1; therefore, issuing the first operand, transit

50

Some additions are shown in FIG. four.

Constant generation mode. In this mode, the field 2.5 of register 2 stores the operation code “Generate a constant, which, arriving at the decoder 9, indicates a single signal at its corresponding output. This signal, arriving at the control input of the switch 10, organizes the looping of the information output and the input of the register 1, and also prohibits the supply

and the result of the STE can occur on the data from the input 25 of the cell to the information-programmed information extraction input of register 1, in addition, hikes 30.1–30.4 cells with different offsets to the second direct and second peers. After the last issue of the information inputs, respectively, elements And 18

The outputs from vykhbdov 30.1-30.4 on the second outputs of all BPS 6.1-6.4 indicate zero signals, which lead to the appearance of a single signal at the output of the OR-NOT 15 element. This signal permits the passage of the next clock pulse through the element 22 of the trigger for the synchronous input of the trigger 4, where the transfer of the ALE 5 is recorded to take it into account in the next data processing step, and through delay elements 22 and 23 and OR 14 - to the inputs of zeroing triggers 3.1–3.3 and to the third inverse of the input element I 19, which leads to a zero signal indication at the output OR 13. This signal, passing through the third inputs of the BZB 6.1-6.4 to the second inputs of the elements OR-NO 35 and AND 36, prohibits the counting mode of the counter 31 and enables the recording of information into this counter on the next negative clock pulse. There is a regular recording of the delay codes from the fields 1.1 -1.4 of register 1 to counters 31, respectively, BPZ 6.1-6.4, similar to that considered. Differentiated delivery of operands, a transit or the result of an SLE 5 to information outputs 30.1–30.4 cells is achieved by the corresponding programming of fields 2.1–2.4 of register 2.

Copies 22 and 23 of the delay and OR 14 are to the inputs of zeroing of the triggers 3.1-3.3 and to the third inverse input of the element AND 19, which leads to the indication of a zero signal at the output of the element OR 13. This signal, going through the third inputs of the BPZ 6.1-6.4 to the second inputs of the elements OR-NO 35 and AND 36, prohibits the counting mode of the counter 31 and permits recording information into this counter by the next negative clock pulse. There is a regular recording of the delay codes from the fields 1.1 -1.4 of register 1 to counters 31, respectively, BPZ 6.1-6.4, similar to that considered. Differentiated delivery of operands, a transit or the result of an SLE 5 to information outputs 30.1–30.4 cells is achieved by the corresponding programming of fields 2.1–2.4 of register 2.

Thus, in this mode, it is possible to issue with different delays to the information outputs of the cell of the first and second operands, transit and the result of the ALE, which is important in organizing programmable systematic structures in which the streams of input operands and intermediate results in the OVS have different and. changing directions. When programming fields 2.1–2.4 of register 2 and outputting informational outputs 30.1–30.4 of PE, only the input operands and the transit from trigger 3.1–3.3 occur only in the implementation of an extended transit operation.

delays for each information

the first exit 30.1-30.4 passes through the cells without processing at the ALE 5. Time diagrams for the main elements of the cell illustrating the operation and transit

ny mode on the example of the operation - "Logic

Some additions are shown in FIG. four.

Constant generation mode. In this mode, the field 2.5 of register 2 stores the operation code “Generate a constant, which, arriving at the decoder 9, indicates a single signal at its corresponding output. This signal, arriving at the control input of the switch 10, organizes looping of the information output and inputs 19, prohibits the transfer of the result of the SLE 5, allows the passage of a constant from register 1 through the OR element 12 to the first information inputs of multiplexers 8.1–8.4 and input to the sixth input of the BPS 6.1 -6.4, closes the element And 37 and opens the element And 38 for the passage of clock pulses through the BPS 6.1-6.4 at the synchronization of the corresponding output multiplexers. Periodic issue occurs.

Secondly, it is connected to the output of the element OR-- NOT, and the output of the first element I is connected to the input of the first delay element, the output of which is connected to the D-trigger synchronous input, the reset input of which is connected to the first inputs of all blocks of the programmed delay, the reset input of the cell and with the first input of the first element OR, the second input of which is connected to the output of the second delay element, the output of the first element

the constants from register 1 to the required OR are connected to the first inverse information input of 30.1–30.4 cells. the house of the second element And with zero inputs. RS-flip-flops, single inputs of which are connected to the outputs of multiplexers of the first group, control inputs of which | 5 are connected to the outputs of the first, second and third groups of the second command register, outputs of the fourth, fifth, sixth and the seventh groups of which are connected to the second inputs from the first to the fourth blocks of the programmable delay, respectively, the first outputs, when generating a constant, are different cell operation modes prohibited. Thus, in this mode, it is possible to periodically output an arbitrary constant recorded in register 1 to any information outputs of 30.1–30.4 cells.

If it is necessary to prohibit the work of a cell in the field 2.5 of register 2, the code "No operation, and on a certain

The output of the decoder 9 is indicated by units of which are connected to a sync input a signal which, acting through the fourth inputs of the BDZ 6.1-6.4 and the first inverse inputs of the elements 37 and 38, prohibits the passage of clock pulses of the corresponding multiplexers of the second group, the first, second The third and fourth informational inputs of which are connected respectively to the input of the second element.

BPZ 6.1-6.4 cut for multi-25 OR synchronous inputs, first, second and third outputs

plexors 8.1-8.4 and thus blocks their work and the work of the cell as a whole.

Claims (2)

Invention Formula RS-flip-flops, the output of the first RS-flip-flop is connected to the first input of the third element OR and the first information input of the arithmetic-logic element, the second information input of which is connected to the cell of the uniform computing 30 output of the second RS-flip-flop and the second input of the third element And, the third input connected to the output of the third RS flip-flop, and the output of the third element OR is connected to the third inputs of all blocks of the programmable delay, the second outputs of the medium that contains the arithmetic logic element, the first register to command, de coder, two delay elements, two groups of multiplexers, with the information inputs of the multiplexers of the first group connected to information inputs whose 35 are connected to the inputs of the element OR- NOT, the fourth input of the third element OR is connected to the first input of the second element OR and the output of the second element AND, the direct input of which is connected to the first output of the arithmetic logic element, the second output of which is connected to the information input of the D-flip-flop, the output of which is connected to the third information the input of the arithmetic logic unit, the second input of the second element OR is connected ki, the output of the program of which is connected to the output of the lower bit of the first command register, the outputs of the first group of which are connected to the inputs of the decoder, the outputs of the group of which are connected to the control inputs of the arithmetic logic unit, the outputs of the second, third, fourth and fifth groups of the first the command register is connected to the control inputs of the multiplexers of the second group, the outputs of ko40 NOT, the fourth input of the third element OR is connected to the first input of the second element OR and the output of the second element AND, the direct input of which is connected to the first output of the arithmetic logic element, the second output of which is connected to the information input of the D-flip-flop, the output of which is connected to the third information the input of the arithmetic logic unit, the second input of the second element OR is connected The second ones are information output-dd with the output of the third element I, the first input of the cell, the output of the first delay element connected to the input of the second delay element, characterized in that, in order to extend the functionality by defining an arbitrary delay which is connected to the output of the lower bit of the second command register, the first direct input of the commutator and the information input of the first command register, the synchronous input of which is connected to the output of the fourth information transfer, it contains the second 50 And, the first input of which is connected to command register, three RS flip-flops, four OR elements, OR-NOT element, five, AND elements, D-flip-flop, NOT element, switch and four programmable delay blocks, with the clock input of the cell with the same input cell, the first input of the fifth element And, the output of which is connected to the synchronous input of the second command register, whose information input is connected to the output of the switch, the second direct input It is connected to the synchronization inputs of the multi- 55 kotor. It is connected to the input of the input of the programmers of the first group and the first input of the cell, the input of the input resolution by the program of the first element I, the second input of which is connected to the second input of the fourth .m of the OR element-- NOT, and the output of the first AND element is connected to the input of the first delay element, the output of which is connected to the D-flip-flop input, the reset input of which is connected to the first inputs of all programmable delay blocks, the cell reset input and the first input first email ment OR, a second input coupled to an output of the second delay element, an output of first OR is connected to the first inverse input of the second element I and with zero inputs of which are connected to the sync input. corresponding multiplexers of the second group, the first, second, third and fourth information inputs of which are connected respectively to the input of the second element 40 NOT, the fourth input of the third element OR is connected to the first input of the second element OR and the output of the second element AND, the direct input of which is connected to the first output of the arithmetic logic element, the second output of which is connected to the information input of the D-flip-flop, the output of which is connected to the third information the input of the arithmetic logic unit, the second input of the second element OR is connected dd with the output of the third element And the first input with the release of the third element And the first input which is connected to the low-order output of the second command register, the first direct input of the commutator and the information input of the first command register, the synchronous input of which is connected to the output of the fourth electrical input of the cell, the first input of the fifth element I, the output of which is connected to the synchronous input of the second command whose information input is connected to the switch output, the second direct input which is connected to the input of the input of the program cell, the input of the input resolution of the program of which is connected to the second input of the fourth element AND and the first input of the third element OR, the output of which is connected to the second input of the fifth element AND, $ the second input of the third element OR is connected to the third direct and inverse inputs of the switch, the inverse input of the second element AND, the second input of the third element AND and the first output of the decoder, the second output of which is connected to the fourth inputs of all the delay programmers, the fifth input where dN soodine- to a clock input of the cell, and sixth programmable delay block moves with oedineny pervsh output decoder. I 2. The cell of claim 1, wherein the programmable delay block contains three AND elements, two OR elements, a meter, a delay element, an OR element, and an RS flip-flop, the first block input connected to the counter reset input , informational inputs of which are connected to the second inputs of the block, the third input of which is connected to the first inputs of the OR-NOT element and the first AND element, the second inputs of which are connected to the output of the first 0 the OR element whose inputs are connected to the counter outputs, the synchronous input of which is connected to the output of the OR element and the zero input of the RS flip-flop, whose single input is connected to the output of the second AND element and the first input of the second OR element, the output of which is connected to the first output of the block whose fourth input is connected to the first inverse and inverse inputs of the second and third AND elements, the first direct inputs of which are connected to the third inputs of the first AND element and the OR-NOT element and the fifth input of the block, the sixth input of which a second inverse oedinen and second direct 5 inputs of the second and third elements AND, the third inverse input of the second element AND is connected to the output of the first element OR and the second output of the block, the second direct input of the second element AND is connected to the output of the delay element whose input is connected to the inverse output of the RS flip-flop, outputs the first and third elements of AND are connected with the subtraction, the input of the counter and the second input of the second element OR. FIG, g